max transition violations

When a signal takes too long transiting from one logic level to another, a transition violation is reported. The violation is a function of the node resistance and capacitance.

Maximum transition time The transition time of a net is the longest time required for its driving pin to change logic values. Transition time is decided on the basis of rise time and fall time. This constraint (max_transition) is based on the library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load.

How to calculate:

CMOS delay model: Transition Time = Drive R X Load C Non­linear delay model: Transition Time from table lookup and interpolation/extrapolation.


You can make the transition time of each net less than the “max_transition” value (defined in the library file) by adding a buffer at the output of driving gate.



If your design uses multiple technology libraries and each has a different default_max_transition value, synthesis tools uses the smallest max_transition value globally across the design.
This info is present in the .lib file (liberty file).

What’s the significance of max_transition in the design? 

 

 Lot of people has different views for this. Like if you will increase the max_transition value then your delay will increase, so library has to characterize for those delay value also and so on. 

 Case 1:

 Power consumption is becoming a major issue. Everyone wants to reduce the power consumption. Powers are of 2 type­ Switching and Leakage power.

 Consider the  inverter shown below consisting of a PMOS  to VCC and  NMOS to GND.

when  input is low the PMOS is  transistor is ON and the n­channel is OFF. It will cause current to flow from VCC and  output is  high state.
When input is high PMOS is OFF and NMOS is ON. It will cause current flows to GND, output is  low.
In both cases there is  no current flows from VCC to GND directly  However, when switching from one state to another, the input crosses the threshold region, causing the n­channel and the p­channel to turn on simultaneously, generating a current path between VCC and GND.

This current surge can be damaging, depending on the length of time that the input is in the threshold region (Low Level threshold to High Level threshold). Now, if the transition time is large means length of time to change the logic is large. So both the channel turns on simultaneously more time. Means more Switching power consumption.


So library characterization team has to come up with a maximum value of transition time either specific to all cells in a particular library or individual cell.

 Case 2:  Frequency dependency

we know that that cell delay is a function of input trans and output load. when input trans is too much cell delay will be increased depends on the library characterization. 

1. when Design is working on high freq (1GHz) and  if there are more number of levels in that path and max_trans limit is too much from the library then we will get the cell delay more, it will cause higher delay for the cell.  

2. when freq is less then even though max_trans limit is more we will not see timing violation because of the cell delay.

It can vary with the operating frequency of a cell. Since this parameter is based on rise/fall time and rise/fall time is the time required to charge/discharge input capacitance load of the pin.

Now if operating frequency vary, the capacitive load vary as per relationship of Xc=1/ωC . If multiple clocks launch the same paths, the most restrictive value is used.  

Now what I am trying to say that max_trans also depends on the freq to meet the tiiming.  we need to set the max_trans limit or interpolate that value so that we will get minimum  cell delay.

Cause of failure of trans 

 

(1) input port transition;

(2) input clock transition; (important)

(3) wire length...

(4) Fanout...

(5) Gate drive strength...

The transition is decided by two factors: one is the input slew (transition), one is output load(including wire cap and fanout).

If anyone of them is over the limit of Lookup Table in std cell library, inaccuracy is produced. So, fixing max_transition violation is inevitable.

If input slew is too slow, increment the driver strength.

If output load is too high, add some buffer.

Now, you need look into these two factors.

Debug if there are any design consistency isses

Use the check_design command to verify the design consistency. The check_design command reports a list of warning and error messages,

By default, the check_design command reports all warning messages. You can reduce the output by summarizing the warnings (by using the -summary option) or by disabling the warnings (by using the -no_warnings option).

you can also use the following method to fix max trans

1. Increase the drive capacity of the book to increase the voltage swing or decrease the capacitance and resistance by moving the source gate closer to sink gate.
2. Increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation