IR Drop

1. Power

The power spent in Complementary metal oxide semiconductor (CMOS) can be classified as dynamic power consumption and leakage or static power consumption.

2. Leakage power:

is consumed at all times even in ideal states and it is dominating total power equation in advanced technologies. It is unnecessary and need to minimize it.

3. Dynamic power consumption:

is due to the low impedance path between the rails formed through the switching devices. The switching at the output of logic gates can be due to desired functional transitions or due to spurious transitions called glitches. The glitches at the output of logic gates are due to differences in arrival times at various inputs. Glitch power in modern circuits account for 20% to 70% and it is 7% to 43%[1] of the dynamic power consumption.

3.1.Glitch and Dynamic Power

Glitches are the spurious transitions which occur due to difference in arrival times of signals at the gate inputs. These are not needed for the correct functioning of the logic circuit. Power consumed by glitches is called as Glitch power. Every signal net of a gate needs to be transmitted at most once in every clock cycle. But in the real scenario there are output transitions switching more than once in every clock cycle and these unnecessary transitions will also consume power and they contribute significantly to unexpected peak currents which are higher than that of original designs specifications. These peak currents occur in a very short period of time and bring about a large transient voltage or IR drop simultaneously.

The IR drop is a power integrity issue and can impact circuit performance and reliability. So it is very advantageous to eliminate glitches in the circuits as power consumption is critical in today’s chips. The flow of glitch in a digital logic circuit gate is shown in Fig . In a logic gate, the number of edges in the transients at the output of the gate may equal to the number of arriving signals at the gate. The maximum difference in the arrival time of the signals at the inputs of the gate is called as differential path delay. It is also the maximum width of the possible glitch at the circuit output. Consider Fig. 1, in the circuit we can see the unbalanced arrival times of the inputs due to the inverter circuit in the lower input path of the NAND gate

4. How will you do power planning?

Unless Power planning is planned out of the design, power integrity issues like excessive rail voltage drop (IR drop) and ground bounce can create timing problems. In addition, electromigration can lead to chip failures. By using best practices to develop a system-on-a-chip's (SoC's) power structure and analyzing it often throughout the design flow, one can ensure power integrity while preventing a variety of layout difficulties.

Power pads supply power to the chip. Power rings carry power around the periphery of the die, a standard cell's core area, and individual hard macros. Typically, the rings are put in higherlevel routing layers to leave lower layers for signal routing.

1. · There are two types of power planning and management. They are core cell power management and I/O cell power management.
2. · In former one VDD and VSS power rings are formed around the core and macro.
3. · In addition to this straps and trunks are created for macros as per the power requirement.
4. · In the later one, power rings are formed for I/O cells and trunks are constructed between core power ring and power pads.
5. · Top to bottom approach is used for the power analysis of flatten design while bottom up approach is suitable for macros.
6. · The power information can be obtained from the front end design.
7. · The synthesis tool reports static power information.
8. · Dynamic power can be calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL description and test bench.
9. · Exhaustive test coverage is required for efficient calculation of peak power. This methodology is depicted in Figure (1).

5. How can you reduce dynamic power?

-Reduce switching activity by designing good RTL

-Clock gating

-Architectural improvements

-Reduce supply voltage

-Use multiple voltage domains-Multi vdd



Most commonly used methodology to resolve peak transient IR drop is to add the decoupling capacitance (Decap) cells in to layout. These Decap cells acts as local charge reservoirs and reduce the effect of peak IR drop on neighbouring circuits. However Decap cells contribute significant gate tunnelling leakage current to the design and starting from 90nm technologies and below this contribution is even more due to gate oxide scaling.

6. What are the vectors of dynamic power?

I & V

Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. Dynamic IR drop Evaluates the IR drop caused when large amounts of circuitry switch simultaneously.

One of the key requisites is to generate a realistic VCD (Value Change Dump) a file format that captures the switching information which accounts for the real cell and interconnect delays typically done by annotating an SDF (Standard Delay Format) in the gate level simulation.

Such a simulation captures the realistic spread of switching activity in the design for duration of time window (T). During dynamic IR drop analysis T will be break down in to several small time steps.

The length of time step will be determined by the switching activity window or average transition time which can be obtained by the static timing analysis.

Do you know about input vector controlled method of leakage reduction?

Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.

7. If you have both IR drop and congestion how will you fix it?

-Spread macros

-Spread standard cells

-Increase strap width

-Increase number of straps

-Use proper blockage