Flip-chip and wire bonding

In the world of high-speed/high-performance package design, the primary packaging solution is flip chip in package (FCiP) technology. It is widely understood that flip chips offer a variety of benefits compared to traditional wire-bond packaging, including superior thermal and electrical performance, the highest I/O capability, substrate flexibility for varying performance requirements, well-established process equipment expertise, proven construction, and reduced form factors. Despite these benefits, flip chips have not been a cost-effective packaging solution.

The costs associated with flip chips stem from wafer fabrication vendors, substrate vendors, and assembly/packaging subcontractors. The increased costs are realized at every step of the process from repassivation and redistribution (RDL) at wafer fabrication, to the high-performance multilayer organic build-up substrates provided by the substrate vendor. With the added costs of assembly, the flip chip package becomes a cost-prohibitive option.

Recently, packaging and assembly houses have taken great steps toward providing cost-effective solutions by offering flip chip packaging options on a standard leadframe (FCSOL), quad flat pack no leads (QFN), and standard bis-maleimide triazine (BT) resin substrates. While there may still be costs upfront in the wafer fabrication process, assembly houses are using proven technologies and innovative processes to provide customers with better solutions.

It is the cost-effective, proven technologies and innovative processes that continue to interest customers and drive designers to maximize package performance. Designers must understand key electrical and thermal performance package challenges, and work to minimize the negative impacts. By maximizing the strengths of the technology, using standard package material sets, robust manufacturing, and assembly processes, the die-up, wire-bonded, plastic overmolded, BT laminate package technology is a viable solution for high-speed design applications.


Flip-chip assembly and wire bonding are the principal methods for interconnecting ICs. While each offers strong advantages in certain types of applications, packaging is continuing to evolve into a segmented marketplace, with several factors dictating the most appropriate means of interconnection.

 

1. Cost, performance and form factor have become the key drivers in selecting between wire bonding and flip-chip bonding as the "preferred" IC interconnecting method.
2. Applications such as cellular telecommunications and wearable portable consumer electronics often require the use of flip-chip packaging for its small form factor and, in some cases, high speed.
3. In other cases, typically with I/Os in the range of 100-600, the existing infrastructure, flexibility and materials/substrate costs of wire bonding provide dominant advantages.
4. Further segmentation is provided by the emergence of several intermediate hybrid interconnect alternatives, such as stud/ball bumping1, gold and aluminum ribbon wedge bonding, under-bump metalization (UBM) that can be both bumped and wire bonded, wafer-level packages (WLP) with and without underfill, Direct-Chip Attach (DCA) or CSP packaging. Wire-bonded CSPs take advantage of the existing infrastructure to produce packages with near-chip-size form factors2.

These alternatives currently are less widely used and will not be addressed in detail in this article

TECHNOLOGY CHOICES

 

INTERCONNECT	PERFORMANCE	FORM FACTOR
WIRE BOND	SIGNAL PROPAGATION	PACKAGING DENSITY
FLIP-CHIP	SIMULTANEOUS SWITCHING	PRODUCT
WAFER CSP	NOISE (SSN)
STUD BUMP	PARASITICS
	POWER AND GROUND DISTRIBUTION
	RELIABILITY
PROCESS ADVANTEGES WIRE BOND FLEXIBILITY INFRASTRUCTURE COST RELIABILITY FLIP-CHIP DEVICE SPEED POWER AND GROUND DISTRIBUTION I/O DENSITY WITH AREA ARRAY PACKAGE SIZE /FORM FACTOR LOW STRESS OVER ACTIVE AREA RELIABILIT ASSEMBLY PROCESS COMPARISON ON ORGANIC SUBSTRATE WIREBOND WAFER DICE DIE ATTACH CURE WIRE BONDING ENCAPSULATE BALL ATTACH MARK SYSTEM TEST FLIP-CHIP WAFER WAFER BUMPING DICE PICK AND PLACE PLUS FLUX REFLOW UNDERFILL ENCAPSULATION BALL ATTACH MARK SYSTEM TEST Advantages In general, the flexibility, infrastructure and cost of wire bonding are its major advantages. Package size is smaller, and device speed is normally higher for flip-chip. System speeds with wire-bonded packages designed for high signal-propagation rates (e.g., RDRAM, BOC), however, remain competitive4. Flip-chip devices often have many more bumps than equivalent wire-bonded devices have bond pads. Because the bumping cost/wafer is fixed (independent of how many bumps there are per wafer), there are electrical advantages to designing in additional bumps. As chip voltages drop and current requirements increase, it is advantageous to distribute power and ground directly to the core of the devices, with area array solder bumps to minimize voltage drop. These low-inductance power and ground paths also minimize SSN (simultaneous switching noise) and ground bounce. On especially sensitive signal paths, additional power and ground bumps can be used to surround the sensitive I/O bump, shielding the bump from noise induced by neighboring circuitry. The Differences The two processes are substantially different from an automation perspective. Wire bonding is best characterized as a single-point-unit operation. Each bond is individually produced. Die on their carrier or substrate are moved through a wire bonder. The machine's pattern recognition system identifies the die, transforms and corrects the taught locations for each bond, and individually moves to each location to produce an interconnection. Flip-chip is a wafer-scale operation. Bumps are formed on an entire wafer, and the wafer is diced; individual die are picked, fluxed and placed on the substrate. The flux must be tacky enough to hold the die in place for handling through reflow. The solder is reflowed above its melting point to form the interconnection. Underfill and encapsulation processes complete the assembly. At all times, the process handles entire wafers, die or substrates. It is never a single-point