1)Dynamic (switching) power dissipation
As the name indicates it occurs when signals which goes through the CMOS circuits change their logic state. At this moment energy is drawn from the power supply to charge up the output node capacitance.Charging up of the output capacitnce causes transition from 0V to Vdd.Considering an
inverter exaple power drawn from the power supply is dissipated as heat in pMOS transitor. On the other hand charge down process causes NMOS transistor to dissipate heat. Output capacitance of the CMOS logic gate consists of below components:
1)Output node capacitance of the logic gate: This is due to the drain diffusion region.
2)Total interconnect capacitance: This has higher effect as technology node shrinks.
3)Input node capacitance of the driven gate: This is due to the gate oxide capacitance.
To find the avearage power energy required to charge up the output node to Vdd and charge down the total output load capacitance to ground level is integrated. Applied input periodic waveform having its period T is assumed to be having zero rise and fall time.
2)Short circuit power consumption
When dynamic power is analyzed the switching component of power consumption, an instantaneous rise time was assumed, which insures that only one of the transistors is ON. In practice, finite rise and fall times results in a direct current path between the supply and ground, GND, this exists for a short period of time during switching.
Short circuit power
Consider an example of inverter. During switching both NMOS and PMOS transistors in the circuit conduct simultaneously for a short amount of time. Specifically, when the condition, VTn (lesser than) Vin (lesser than) Vdd - |VTp| holds for the input voltage, where VTn and VTp are NMOS and PMOS thresholds, there will be a conductive path open between Vdd and GND because both the NMOS and PMOS devices will be simultaneously on (also known as slew ) . This forms direct current path between the power supply and the ground. This current has no contribution towards charging of the output capacitance of the logic gate.
When the input rising voltage exceeds the threshold voltage of NMOS transistor, it starts conducting. Similarly until input voltage reaches Vdd-|Vt,p| PMOS transistor remains ON. Thus for some time both transistors are ON. Similar event causes short circuit current to flow when signal is falling. Short circuit current terminates when transition is completed.
Assuming symmetric inverter with Kn=Kp=K and Vt,n=|Vt,p|=Vt and very small capacitive load and both rise and fall times are same we can write,
Pavg(short circuit) = 1/12.k.τ.Fclk.(Vdd-2Vt)3 [1]
Thus short circuit power is directly proportional to rise time, fall time and k. Therefore reducing the input transition times will decrease the short circuit current component. But propagation delay requirements have to be considered while doing so.
Short circuit currents are significant when the rise/fall time at the input of a gate is much larger than the output rise/ fall time. This is because the short-circuit path will be active for a longer period of time. To minimize the total average short-circuits current, it is desirable to have equal input and output edge times [2]. In this case, the power consumed by the short-circuit currents is typically less than 10% of the total dynamic power. An important point to note is that if the supply is lowered to be below the sum of the thresholds of the transistors, Vdd (lesser than) VTn + |VTp|, the short-circuit currents can be eliminated because both devices will not be on at the same time for any value of input voltage.
3)Static (Leakage) power consumption
•P(leakage) = f (Vdd, Vth, W/L)
Where Vdd = supply voltage,
Vth = threshold voltage,
W = transistor width,
L = transistor length
The power consumed by the subthreshold currents and by reverse biased diodes in a CMOS transistor are considered as leakage power.The leakage power of a CMOS logic gate does not depend on input transition or load capacitance abd hence it remains constant for a logic cell.
• I1: Diode reverse bias current
• I2: Sub-threshold current
• I3: Gate-induced drain leakage
• I4: Gate oxide leakage
Reverse Biased Diode Current :
Parasitic diodes formed between the diffusion region of the transistor and substrate consume power in the form of reverse bias current which is drwn from the power supply.
I inverter when input is high NMOS transistor is ON and output voltage is discharged to zero. Now between
drain and the n-well a reverse potential difference of Vdd is established whcih causes diode leakage through
the drain junction.
The n-well region of the PMOS transistor w.r.to. p-type sustrate is also reverse biased. This also leads to leakage current at the N-well junction. The reverse current can be mathematically expressed as,
Ireverse=A.Js.(exp(q.Vbias/kT)-1)
where,
Vbias-->reverse bias voltage across the junction
Js-->reverse satuartion current density
A-->junction area
Subthreshold CurrentThe subthreshold current always flow from source to drain even if the gate to source voltage is lesser than the threshold voltage of the device. This happens due to the carier diffusion between the source and drain regions of the CMOS tranistor in weak inversion.
When gate to source voltage is smaller than but very close to threshold voltage of the device then subthreshold current becomes significant.
minimization of subthreshold leakage:
A increase in the threshold voltage of the device keeps the Vgs of the NMOS transistor safely below the Vt,n. This is the case for logic zero input. For the logic one input increase in the threshold voltage of the device keeps the Vgs of the PMOS transistor safely below the Vt,p.
Fix Method for static, Dynamic and leakage
- Changing existing layer or via resistivity
- Adding a power/ground pad
- Deleting a power/ground pad
- Adding a via
- Deleting a via
- Adding a power strap
- Editing/deleting a power strap
- Adding a decap cell
- Adding metal layers and via or via arrays
- Writing an ECO file
- Reading an ECO file
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