With the development of VLSI (Very Large Scale Integration), designers are more and more in pursue of higher performance, less power consumption and smaller chip area. In this requirement, the process becomes more advanced by the foundry, such as 28nm and even 20nm. However, getting better PPA (performance, power, area), it also introduces some problems the designer must face to.Timing library modeling is one of them.
In advanced node, the behavior of transistor becomes more and more complex. Traditional NLDM (Non-liner Delay Model) is no longer suitable to present the accuracy. Instead, ECSM (Effective Current Source Mode) and CCS (Composite Current Source) are two popular models in library
characterization.
In advanced process nodes like 28nm and below the delay calculation is greatly affected by new physical phenomena which we call waveform effects. The factors contributing to the waveform effects include crosstalk, strong resistive shielding of wires, and nonlinear capacitance of receivers. In order to meet the accuracy requirements the modern delay calculation needs to use a simulation-based infrastructure and sophisticated gate delay models. A thorough validation and tuning of Cadence’s new delay calculator called Advanced Analysis Engine (AAE) is a key part of its development and productization. Most of the accuracy validations performed internally and by customers use sets of small hand-created circuits with different driver/receiver cells, wire parameters, etc. There has been therefore a strong need in a utility which could automatically create set of small circuits, run our STA flow and device level simulator and generate a table with results.
It can be enabled in Cadence SOC Encounter as:
setDelayCalMode -engine aae -SIAware true
In advanced node, the behavior of transistor becomes more and more complex. Traditional NLDM (Non-liner Delay Model) is no longer suitable to present the accuracy. Instead, ECSM (Effective Current Source Mode) and CCS (Composite Current Source) are two popular models in library
characterization.
In advanced process nodes like 28nm and below the delay calculation is greatly affected by new physical phenomena which we call waveform effects. The factors contributing to the waveform effects include crosstalk, strong resistive shielding of wires, and nonlinear capacitance of receivers. In order to meet the accuracy requirements the modern delay calculation needs to use a simulation-based infrastructure and sophisticated gate delay models. A thorough validation and tuning of Cadence’s new delay calculator called Advanced Analysis Engine (AAE) is a key part of its development and productization. Most of the accuracy validations performed internally and by customers use sets of small hand-created circuits with different driver/receiver cells, wire parameters, etc. There has been therefore a strong need in a utility which could automatically create set of small circuits, run our STA flow and device level simulator and generate a table with results.
It can be enabled in Cadence SOC Encounter as:
setDelayCalMode -engine aae -SIAware true
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