Litho based Routing

 

Litho based routing can be understand from the below Dig, It is implemented below 28nm:

An automated flow has been implemented to detect printability hotspots using a model-based solution, and to automatically fix these hotspots during final routing optimization. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. Since the semiconductor industry is currently limited to 193nm scanners, no relief is expected from the equipment side and must come from the design side. Rule-driven routers fail to capture hotspots, as they are based on ideal polygons that do not represent the real silicon image. Model-based hotspot detection can validate design manufacturability and will account for complex two-dimensional effects that stem from aggressive scaling of 193nm lithography. To enable this solution, manufacturing teams started to release model-based lithography checks; initially as a service using the manufacturing flow to check small cells, and now by releasing process information to designers for full-chip lithography hotspot detection. However, if manual fixing is manageable at the cell level, hotspot removal in large placed and routed blocks or even full chip is more challenging. Not only is full-chip litho/etch simulation required to have a reasonable runtime, but the fixing solution needs to be connectivity-aware and incremental with a very fine step size. This is required for a timing-aware solution that mitigates hotspots without adversely affecting timing closure. The automated flow links a hotspot detection solution and a chip routing optimization tool. The hotspot detection solution passes the hotspot locations and associated fixing guidelines to the chip routing optimization tool. The chip routing optimization tool removes the hotspots in an incremental fashion so as to have no significant impact on timing, but a significant impact on printability. This process of checking for hotspots and incrementally fixing them is iterated until a hotspot-free design is achieved. This paper describes how fabless designers have integrated this hotspot detection solution in their design flow and how the hotspot removal flow efficiently removed most hotspots in real designs, thereby providing DFM closure.

It Provides capabilities at implementation phase to prevent ,detect and fix lithography issues. In this process we need to have technology files and flow options to have litho friendly vias, shielding and U-shapes litho aware routing. It does a pattern matching hot spot detection on the P&R database and does a Hot spot repair.

  

It can be defined as:

1. Provide litho checks at sign off phase
2. Pattern matching hot spot detection
3. OPC and litho simulation
4. Auto-correction rate calculation 

 Prob and sol:

After repair