PCB-Package-Die Chip flow

Package level

 SOC total pin counts surpassing 30,000
• IO pad-ring generation no longer a simple task.
• Staggered, multi-row placement
• Area IO placement
• Flip-chip development
• Managing, placing and optimizing bumps
• RDL routing
• High Speed serial I/Os
• I/O buffer scaling for minimum power
• Interconnect modeling across package and PCB
• Power delivery across PCB, Package and IC
• Trade off analysis between wire bond and flip-chip
• More accurate 3D (full-wave) analysis for package and PCB interconnect structures
• Package costs killing profit margin
• Drive to standard packages
• Package selection no longer an afterthought
• PCB layout is a bottle-neck to volume
• Interconnect/Routing problems on the PCB are amplified by the high pin count devices.
• Additional layers driving up cost

IC level

• I/Os
• Peripheral (including multi-row stagger)
• Area (including direct bumping)
• Bumps (C4s)
• Interposer
• Package level
• Bumps (C4s)
• Bond fingers
• Package pins
• Interposers
• PCB level
• Package pins (including breakouts)