Constraint Reports in PT(prime time report_constraints -all_violators)

The report_constraint command summarizes the constraint violations, including the amount by which a constraint is violated or met and the design object that is the worst violator. PrimeTime can report the maximum area of a design and certain timing constraints. It can also verify whether the netlist meets specific pin limits.

Timing Constraints

There are several types of timing constraints, such as

Maximum path delay and setup

Minimum path delay and hold

Recovery time, the minimum amount of time required between an asynchronous control signal (such as the asynchronous clear input of a flip-flop) going inactive and a subsequent active clock edge

Removal time, the minimum amount of time required between a clock edge that occurs while an asynchronous input is active and the subsequent removal of the asserted asynchronous control signal

Clock-gating setup and hold

Minimum pulse width high or low at one or several clock pins in the network

Minimum period at a clock pin

Maximum skew between two clock pins of a cell

reference solvnet/prime time