Level Shifter in VLSI Chip Design

Level Shifter cell is used to shift a signal voltage range from one voltage domain to another. This is required when the chip is operating at multiple voltage domains. A signal in one voltage domain may have a voltage range which is different to the signal in another voltage domain. This difference in the voltage range may cause unreliable functioning of the destination domain. Hence Level shifter cells are inserted in the voltage domain crossings.



In the picture above the signal from the 0.7V domain drives a logic cell operating in the 1V volatge domain. The 0.7 V domain spends more time in the threshold voltage of the 1V voltage logic cell which may cause unacceptable timing delays and crowbar currents. If the voltage difference is bigger it may happen that the lower voltage range signal may not even get to the threshold voltage of the higher voltage domain logic cell. A level shifter cell in the voltage domain crossover ensures a reliable functioning of the multi-voltage domain chip.

There are two possible situations, one where the source signal voltage is low compared to the sink voltage domain, second one is vice verse. But there can be also situations where dynamic voltage scaling is used and the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high and high to low. Accordingly the three types of level shifters are,



Low to High Level ShifterHigh to Low Level ShifterBoth Low to High and High to Low Level Shifter


Low to High Level Shifters can be realized using a buffer or a pair of inverters. The gate voltage of a MOS transistor can be driven up to its breakdown voltage. Breakdown voltage is the voltage beyond which the dielectric gets damaged irreversibly and no longer exhibits the desired dielectric characteristics. This breakdown voltage is typically much higher than the supply voltage. This means the input of the MOS transistor can be driven with an higher voltage than the supply voltage (provided gate voltage is bellow its breakdown voltage).



In the picture shown above the positive gate voltage when it exceeds the Breakdown voltage the dielectric breaks and starts conducting. This is because the dielectric was unable to withstand the voltage stress after a certain voltage level. So a buffer can be used as High to Low Level Shifter if the High voltage signal does not reach its breakdown voltage.



Low to High Level shifter requires a careful transistor sizing. A low voltage signal may not even reach the threshold voltage of the logic cell in the High voltage domain. In this case the level shifter circuit is built by choosing the transistor sizing to bring the threshold voltage down so that the low voltage signal can turn it ON. Also they may increase the GATE thickness to help accumulate the charge better. Traditional Low to High Level Shifter circuit used a cross coupled transistor to amplify the low voltage signal. It consumes more power and introduces more delay. However the designers have come up with many different and efficient ways to implement the Low to High Level Shifter. The circuit implementation of a typical Low to High Level Sifter is show in the picture below.



In the circuit shown above, the P1, P2, N1 and N2 form a cross coupled amplifier which is driven by the low voltage input signal. The transistor size of P1, P2, N1 and N2 are chosen such that the Level Shifter circuit operates reliably for the desired input and output voltage levels. The same circuit can be used for High to Low conversion also. Again the High voltage domain signal should not exceed the gate breakdown voltage. The Level Shifter cell is characterized in all the possible voltages of input and supply and a reliable operating range is derived.