Design Rule Chekcs (DRC )

Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that determines whether a particular chip layout satisfies a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verification of the design, which also involves LVS (Layout versus schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.

1) Logic DRC contain following three points:

1. Net fanout
2. Net capacitance
3. Net transition

FIXING TECHNIQUES: 

1. MAX TRANSITION

1. ADD A BUFFER IN MIDDLE OF THE LONG LENGTH WIRE.
2. REDUCE THE WIRE LENGTH.
3. ADDING A CHAIN OF BUFFERS.

2. MAX CAPACITANCE:

1. DECREASE WIRE LENGTH AT OUTPUT SIDE.

3. MAX FANOUT:

1.  CLONNING=ADDING A SAME CELL LOAD WILL BE DIVIDED.
2. SHARING THE LOAD

 2) Physical DRC contain various rule, and it's depends on technology, it is described in technology file (tf file), tf file example:

Usually contain technology information such as:MinWdith of all Layers

1. Fat Metal Width Spacing Rule
2. Fat Metal Extension Spacing Rule
3. Maximum Number Minimum Edge Rule
4. Adjacent Via Rule
5. Fat Metal Contact Rule
6. Fat Metal Extension Contact Rule

Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of his or her mask set. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly. The most basic design rules are shown in the diagram on the right. The first are single layer rules. A width rule specifies the minimum width of any shape in the design. A spacing rule specifies the minimum distance between two adjacent objects. These rules will exist for each layer of semiconductor manufacturing process, with the lowest layers having the smallest rules (typically 100 nm as of 2007) and the highest metal layers having larger rules (perhaps 400 nm as of 2007). A two layer rule specifies a relationship that must exist between two layers. For example, an enclosure rule might specify that an object of one type, such as a contact or via, must be covered, with some additional margin, by a metal layer. A typical value as of 2007 might be about 10 nm. There are many other rule types not illustrated here. A minimum area rule is just what the name implies. Antenna rules are complex rules that check ratios of areas of every layer of a net for configurations that can result in problems when intermediate layers are etched. Many other such rules exist and are explained in detail in the documentation provided by the semiconductor manufacturer. Academic design rules are often specified in terms of a scalable parameter, λ, so that all geometric tolerances in a design may be defined as integer multiples of λ. This simplifies the migration of existing chip layouts to newer processes. Industrial rules are more highly optimized, and only approximate uniform scaling. Design rule sets have become increasingly more complex with each subsequent generation of semiconductor process.

 

 

LVS