Tuesday 14 October 2014

Flip-chip and wire bonding

In the world of high-speed/high-performance package design, the primary packaging solution is flip chip in package (FCiP) technology. It is widely understood that flip chips offer a variety of benefits compared to traditional wire-bond packaging, including superior thermal and electrical performance, the highest I/O capability, substrate flexibility for varying performance requirements, well-established process equipment expertise, proven construction, and reduced form factors. Despite these benefits, flip chips have not been a cost-effective packaging solution.





The costs associated with flip chips stem from wafer fabrication vendors, substrate vendors, and assembly/packaging subcontractors. The increased costs are realized at every step of the process from repassivation and redistribution (RDL) at wafer fabrication, to the high-performance multilayer organic build-up substrates provided by the substrate vendor. With the added costs of assembly, the flip chip package becomes a cost-prohibitive option.

Recently, packaging and assembly houses have taken great steps toward providing cost-effective solutions by offering flip chip packaging options on a standard leadframe (FCSOL), quad flat pack no leads (QFN), and standard bis-maleimide triazine (BT) resin substrates. While there may still be costs upfront in the wafer fabrication process, assembly houses are using proven technologies and innovative processes to provide customers with better solutions.

It is the cost-effective, proven technologies and innovative processes that continue to interest customers and drive designers to maximize package performance. Designers must understand key electrical and thermal performance package challenges, and work to minimize the negative impacts. By maximizing the strengths of the technology, using standard package material sets, robust manufacturing, and assembly processes, the die-up, wire-bonded, plastic overmolded, BT laminate package technology is a viable solution for high-speed design applications.


Flip-chip assembly and wire bonding are the principal methods for interconnecting ICs. While each offers strong advantages in certain types of applications, packaging is continuing to evolve into a segmented marketplace, with several factors dictating the most appropriate means of interconnection.
 
  1. Cost, performance and form factor have become the key drivers in selecting between wire bonding and flip-chip bonding as the "preferred" IC interconnecting method.
  2. Applications such as cellular telecommunications and wearable portable consumer electronics often require the use of flip-chip packaging for its small form factor and, in some cases, high speed.
  3. In other cases, typically with I/Os in the range of 100-600, the existing infrastructure, flexibility and materials/substrate costs of wire bonding provide dominant advantages.
  4. Further segmentation is provided by the emergence of several intermediate hybrid interconnect alternatives, such as stud/ball bumping1, gold and aluminum ribbon wedge bonding, under-bump metalization (UBM) that can be both bumped and wire bonded, wafer-level packages (WLP) with and without underfill, Direct-Chip Attach (DCA) or CSP packaging. Wire-bonded CSPs take advantage of the existing infrastructure to produce packages with near-chip-size form factors2.
These alternatives currently are less widely used and will not be addressed in detail in this article


TECHNOLOGY CHOICES

 
INTERCONNECT
PERFORMANCE
FORM FACTOR
WIRE BOND
SIGNAL PROPAGATION
PACKAGING DENSITY
FLIP-CHIP
SIMULTANEOUS SWITCHING
PRODUCT
WAFER CSP
NOISE (SSN)
 
 
 
 
STUD BUMP
PARASITICS
 
 
POWER AND GROUND DISTRIBUTION
RELIABILITY
 

PROCESS ADVANTEGES

WIRE BOND
  1. FLEXIBILITY
  2. INFRASTRUCTURE
  3. COST
  4. RELIABILITY
FLIP-CHIP
  1. DEVICE SPEED
  2. POWER AND GROUND DISTRIBUTION
  3. I/O DENSITY WITH AREA ARRAY
  4. PACKAGE SIZE /FORM FACTOR
  5. LOW STRESS OVER ACTIVE AREA
  6. RELIABILIT


ASSEMBLY PROCESS COMPARISON ON ORGANIC SUBSTRATE

WIREBOND
  1. WAFER
  2. DICE
  3. DIE ATTACH
  4. CURE
  5. WIRE BONDING
  6. ENCAPSULATE
  7. BALL ATTACH
  8. MARK
  9. SYSTEM TEST
FLIP-CHIP
  1. WAFER
  2. WAFER BUMPING
  3. DICE
  4. PICK AND PLACE PLUS FLUX
  5. REFLOW
  6. UNDERFILL ENCAPSULATION
  7. BALL ATTACH
  8. MARK
  9. SYSTEM TEST




Advantages

In general, the flexibility, infrastructure and cost of wire bonding are its major advantages. Package size is smaller, and device speed is normally higher for flip-chip. System speeds with wire-bonded packages designed for high signal-propagation rates (e.g., RDRAM, BOC), however, remain competitive4. Flip-chip devices often have many more bumps than equivalent wire-bonded devices have bond pads.

Because the bumping cost/wafer is fixed (independent of how many bumps there are per wafer), there are electrical advantages to designing in additional bumps. As chip voltages drop and current requirements increase, it is advantageous to distribute power and ground directly to the core of the devices, with area array solder bumps to minimize voltage drop.

These low-inductance power and ground paths also minimize SSN (simultaneous switching noise) and ground bounce. On especially sensitive signal paths, additional power and ground bumps can be used to surround the sensitive I/O bump, shielding the bump from noise induced by neighboring circuitry.



The Differences

The two processes are substantially different from an automation perspective. Wire bonding is best characterized as a single-point-unit operation. Each bond is individually produced.

Die on their carrier or substrate are moved through a wire bonder. The machine's pattern recognition system identifies the die, transforms and corrects the taught locations for each bond, and individually moves to each location to produce an interconnection.

Flip-chip is a wafer-scale operation. Bumps are formed on an entire wafer, and the wafer is diced; individual die are picked, fluxed and placed on the substrate.

The flux must be tacky enough to hold the die in place for handling through reflow. The solder is reflowed above its melting point to form the interconnection. Underfill and encapsulation processes complete the assembly. At all times, the process handles entire wafers, die or substrates. It is never a single-point 

Thursday 9 October 2014

cadence help command



To access the product documentation in HTML and PDF, type 'cdnshelp'
at the system prompt.
For a list of available commands, type 'help'.
To view a man page for a command, type 'man '.
To view a man page for an error message, type 'man '.
For a list of all possible object types, type 'get_attribute -help'.
For a list of all available attributes by object type, type
'get_attribute * -help'.
For a list of all attributes for every object type, type
'get_attribute * * -help'
To list only writable attributes, substitute 'get_attribute' with
'set_attribute'.
To get a template script to run RTL Compiler, use the 'write_template'
command.
To get a template script to run Conformal based on the current RTL
Compiler session, use the 'write_do_lec' command.

Obsolete attributes in the current tool version.
To learn more, type 'get_attribute -help

Clock Uncertainty

You can model the expected uncertainty (skew) for a prelayout design with setup or hold and rise or fall uncertainty values.
  1. PrimeTime subtracts a setup uncertainty value from the data required time when it checks setup time (maximum paths).
  2. PrimeTime adds a hold uncertainty value to the data required time when it checks the hold time (minimum paths).
 
If you specify a single uncertainty value, PrimeTime uses it for both setup checks and hold checks.
 
You can specify the uncertainty or skew characteristics of clocks by using the set_clock_uncertainty command. The command specifies the amount of time variation in successive edges of a clock or between edges of different clocks. It captures the actual or predicted clock uncertainty.  
 
You can specify simple clock uncertainty or interclock uncertainty. Simple uncertainty is the variation in the generation of successive edges of a clock with respect to the exact, nominal times. You specify one or more objects, which can be clocks, ports, or pins. The uncertainty value applies to all capturing latches clocked by the specified clock or whose clock pins are in the fanout of the specified ports or pins.
 
Interclock uncertainty is more specific and flexible, supporting different uncertainties between  clock domains. It is the variation in skew between edges of different clocks.
You specify a “from” clock using the -from, -rise_from, or -fall_from option and a “to” clock the -to, -rise_to, or -fall_to option. The interclock uncertainty value applies to paths that start at the “from” clock and end at the “to” clock. Interclock uncertainty is relevant when the source and destination registers are clocked by different clocks.
You can define uncertainty similarly between two clock pins driven from the same clock, or you can define it as an interclock uncertainty between two registers with different clocks, as shown in Figure
 
 Example of Interclock Uncertainty
 
  
When performing a setup or hold check, PrimeTime adjusts the timing check according to the worst possible difference in clock edge times. For example, for a setup check, it subtracts the  uncertainty value from the data required time, thus requiring the data to arrive sooner by that amount, to account for a late launch and an early capture with the worst clock skew. 
 
When a path has both simple clock uncertainty and interclock uncertainty, the interclock uncertainty value is used, for example  
pt_shell> set_clock_uncertainty 5 [get_clocks CLKA]
 
pt_shell> set_clock_uncertainty 2 -from [get_clocks CLKB] \
 
-to [get_clocks CLKA]
 
When the path is from CLKB to CLKA, the interclock uncertainty value 2 is used.
 
The following commands specify interclock uncertainty for all possible interactions of clock
 
domains. If you have paths from CLKA to CLKB, and CLKB to CLKA, you must specify the
 
uncertainty for both directions, even if the value is the same. For example,
 
pt_shell> set_clock_uncertainty 2 -from [get_clocks CLKA] \
 
-to [get_clocks CLKB]
 
pt_shell> set_clock_uncertainty 2 -from [get_clocks CLKB] \
 
-to [get_clocks CLKA]
 
To set simple clock uncertainty (setup and hold) for all paths leading to endpoints clocked by  
U1/FF*/CP, enter
 
pt_shell> set_clock_uncertainty 0.45 [get_pins U1/FF*/CP]
 
To set a simple setup uncertainty of 0.21 and a hold uncertainty of 0.33 for all paths leading to endpoints clocked by CLK1, enter
 
pt_shell> set_clock_uncertainty -setup 0.21 [get_clocks CLK1]
 
pt_shell> set_clock_uncertainty -hold 0.33 [get_clocks CLK1]
 
To remove clock uncertainty information from clocks, ports, pins, or cells, or between specified clocks, use the remove_clock_uncertainty command removes uncertainty.
 

Wednesday 8 October 2014

DIFFERENT TYPE OF CELLS

STDCELLS-------------------->Nothing But Base cells(Gates,flops).

TAP CELLS-------------------->Avoids Latch up Problem(Placing these cells with a particular distance).

TIE CELLS--------------------->It is used for preventing Damage of cells; Tie High cell(Gate One input is connected to Vdd, another input is connected to signal net);Tie low cells Gate one input is connected to Vss, another input is connected to signal .

END CAP CELLS------------->To Know the end of the row,and At the edges endcap cells are placed to avoid the cells damages at the end of the row to avoid wrong laser wavelength for correct manufacturing.

DECAP CELLS---------------->Charge Sharing;To avoid the Dynamic IR drop ,charge stores in the cells and release the charge to Nets.

ICG CELLS----------------------->Clock gating cells ,to avoid Dynamic power Dissipation.

POWER GATING CELLS---->Power gating to avoid static power Dissipation.

PAD CELLS ----------------------->To Interface with outside Devices;Input to of Power,Clock,Pins are connected to pad cells and outside also.

CORNER CELLS---------------->Corner Pads are used for Well Continity.

Macro cells------------------------->Memories.

Spare Cells-------------------------->Used at the ECO.

Pad filler cells----------------------->Used for Well Continity,placed in between Pads,Std cells.

JTAG CELLS---------------------->These are used to check the IO connectivity.

Monday 6 October 2014

Advanced Analysis Engine : AAE Timing Engine

With the development of VLSI (Very Large Scale Integration), designers are more and more in pursue of higher performance, less power consumption and smaller chip area. In this requirement, the process becomes more advanced by the foundry, such as 28nm and even 20nm. However, getting better PPA (performance, power, area), it also introduces some problems the designer must face to.Timing library modeling is one of them.


In advanced node, the behavior of transistor becomes more and more complex. Traditional NLDM (Non-liner Delay Model) is no longer suitable to present the accuracy. Instead, ECSM (Effective Current Source Mode) and CCS (Composite Current Source) are two popular models in library
characterization. 


In advanced process nodes like 28nm and below the delay calculation is greatly affected by new physical phenomena which we call waveform effects. The factors contributing to the waveform effects include crosstalk, strong resistive shielding of wires, and nonlinear capacitance of receivers. In order to meet the accuracy requirements the modern delay calculation needs to use a simulation-based infrastructure and sophisticated gate delay models. A thorough validation and tuning of Cadence’s new delay calculator called Advanced Analysis Engine (AAE) is a key part of its development and productization. Most of the accuracy validations performed internally and by customers use sets of small hand-created circuits with different driver/receiver cells, wire parameters, etc. There has been therefore a strong need in a utility which could automatically create set of small circuits, run our STA flow and device level simulator and generate a table with results.

It can be enabled in Cadence SOC Encounter as:

setDelayCalMode -engine aae -SIAware true

Wednesday 1 October 2014

Semiconductor Lithography


Semiconductor Lithography (Photolithography) - The Basic Process

 
The fabrication of an integrated circuit (IC) requires a variety of physical and chemical processes performed on a semiconductor (e.g., silicon) substrate. In general, the various processes used to make an IC fall into three categories: film deposition, patterning, and semiconductor doping. Films of both conductors (such as polysilicon, aluminum, and more recently copper) and insulators (various forms of silicon dioxide, silicon nitride, and others) are used to connect and isolate transistors and their components. Selective doping of various regions of silicon allow the conductivity of the silicon to be changed with the application of voltage. By creating structures of these various components millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Fundamental to all of these processes is lithography, i.e., the formation of three-dimensional relief images on the substrate for subsequent transfer of the pattern to the substrate.


The word lithography comes from the Greek lithos, meaning stones, andgraphia, meaning to write. It means quite literally writing on stones. In the case of semiconductor lithography (also called photolithography) our stones are silicon wafers and our patterns are written with a light sensitive polymer called a photoresist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated at least 10 times, but more typically are done 20 to 30 times to make one circuit. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators, and selectively doped regions are built up to form the final device.

The importance of lithography can be appreciated in two ways. First, due to the large number of lithography steps needed in IC manufacturing, lithography typically accounts for about 30 percent of the cost of manufacturing. Second, lithography tends to be the technical limiter for further advances in feature size reduction and thus transistor speed and silicon area. Obviously, one must carefully understand the trade-offs between cost and capability when developing a lithography process. Although lithography is certainly not the only technically important and challenging process in the IC manufacturing flow, historically, advances in lithography have gated advances in IC cost and performance.

Optical lithography is basically a photographic process by which a light sensitive polymer, called a photoresist, is exposed and developed to form three-dimensional relief images on the substrate. In general, the ideal photoresist image has the exact shape of the designed or intended pattern in the plane of the substrate, with vertical walls through the thickness of the resist. Thus, the final resist pattern is binary: parts of the substrate are covered with resist while other parts are completely uncovered. This binary pattern is needed for pattern transfer since the parts of the substrate covered with resist will be protected from etching, ion implantation, or other pattern transfer mechanism.

The general sequence of processing steps for a typical photolithography process is as follows: substrate preparation, photoresist spin coat, prebake, exposure, post-exposure bake, development, and postbake. A resist strip is the final operation in the lithographic process, after the resist pattern has been transferred into the underlying layer. This sequence is shown diagrammatically in Figure 1-1, and is generally performed on several tools linked together into a contiguous unit called a lithographic cluster. A brief discussion of each step is given below, pointing out some of the practical issues involved in photoresist processing. More on these topics will be discussed in detail in subsequent chapters.




1. Substrate Preparation

Substrate preparation is intended to improve the adhesion of the photoresist material to the substrate. This is accomplished by one or more of the following processes: substrate cleaning to remove contamination, dehydration bake to remove water, and addition of an adhesion promoter. Substrate contamination can take the form of particulates or a film and can be either organic or inorganic. Particulates result in defects in the final resist pattern, whereas film contamination can cause poor adhesion and subsequent loss of linewidth control. Particulates generally come from airborne particles or contaminated liquids (e.g., dirty adhesion promoter). The most effective way of controlling particulate contamination is to eliminate their source. Since this is not always practical, chemical/mechanical cleaning is used to remove particles. Organic films, such as oils or polymers, can come from vacuum pumps and other machinery, body oils and sweat, and various polymer deposits leftover from previous processing steps. These films can generally be removed by chemical, ozone, or plasma stripping. Similarly, inorganic films, such as native oxides and salts, can be removed by chemical or plasma stripping. One type of contaminant – adsorbed water – is removed most readily by a high temperature process called a dehydration bake.

A dehydration bake, as the name implies, removes water from the substrate surface by baking at temperatures of 200°C to 400°C, usually for 30 to 60 minutes. The substrate is then allowed to cool (preferably in a dry environment) and coated as soon as possible. It is important to note that water will re-adsorb on the substrate surface if left in a humid (non-dry) environment. A dehydration bake is also effective in volatilizing organic contaminants, further cleaning the substrate. Often, the normal sequence of processing steps involves some type of high temperature process immediately before coating with photoresist, for example thermal oxidation. If the substrate is coated immediately after the high temperature step, the dehydration bake can be eliminated. A typical dehydration bake, however, does not completely remove water from the surface of silica substrates (including silicon, polysilicon, silicon oxide, and silicon nitride). Surface silicon atoms bond strongly with a monolayer of water forming silanol groups (SiOH). Bake temperatures in excess of 600°C are required to remove this final layer of water [1.1]. Further, the silanol quickly reforms when the substrate is cooled in a non-dry environment. Since this approach is impractical, the preferred method of removing this silanol is by chemical means.
Figure 1-1. Example of a typical sequence of lithographic processing steps (with no post-exposure bake in this case), illustrated for a positive resist.
 
Adhesion promoters are used to react chemically with surface silanol and replace the -OH group with an organic functional group that, unlike the hydroxyl group, offers good adhesion to photoresist. Silanes are often used for this purpose, the most common being hexamethyl disilizane (HMDS) [1.2]. (As a note, HMDS adhesion promotion was first developed for fiberglass applications, where adhesion of the resin matrix to the glass fibers is important.) The HMDS can be applied by spinning a diluted solution (10-20% HMDS in cellosolve acetate, xylene, or a fluorocarbon) directly on to the wafer and allowing the HMDS to spin dry (HMDS is quite volatile at room temperature). If the HMDS is not allowed to dry properly dramatic loss of adhesion will result. Although direct spinning is easy, it is only effective at displacing a small percentage of the silanol groups. By far the preferred method of applying the adhesion promoter is by subjecting the substrate to HMDS vapor, usually at elevated temperatures and reduced pressure. This allows good coating of the substrate without excess HMDS deposition, and the higher temperatures cause more complete reaction with the silanol groups. Once properly treated with HMDS the substrate can be left for up to several days without significant re-adsorption of water. Performing the dehydration bake and vapor prime in the same oven gives optimum performance.

 

2. Photoresist Coating

A thin, uniform coating of photoresist at a specific, well controlled thickness is accomplished by the seemingly simple process of spin coating. The photoresist, rendered into a liquid form by dissolving the solid components in a solvent, is poured onto the wafer, which is then spun on a turntable at a high speed producing the desired film. Stringent requirements for thickness control and uniformity and low defect density call for particular attention to be paid to this process, where a large number of parameters can have significant impact on photoresist thickness uniformity and control. There is the choice between static dispense (wafer stationary while resist is dispensed) or dynamic dispense (wafer spinning while resist is dispensed), spin speeds and times, and accelerations to each of the spin speeds. Also, the volume of the resist dispensed and properties of the resist (such as viscosity, percent solids, and solvent composition) and the substrate (substrate material and topography) play an important role in the resist thickness uniformity. Further, practical aspects of the spin operation, such as exhaust, temperature and humidity control, and spinner cleanliness often have significant effects on the resist film. Figure 1-2 shows a generic photoresist spin coat cycle. At the end of this cycle a thick, solvent-rich film of photoresist covers the wafer, ready for post-apply bake.

Although theory exists to describe the spin coat process rheologically, in practical terms the variation of photoresist thickness and uniformity with the process parameters must be determined experimentally. The photoresist spin speed curve (Figure 1-3) is an essential tool for setting the spin speed to obtain the desired resist thickness. The final resist thickness varies as one over the square root of the spin speed and is roughly proportional to the liquid photoresist viscosity.
 
Figure 1-2. Pictorial representation of a simple photoresist spin coat cycle. If w 1 > 0, the dispense is said to be dynamic.
 


Figure 1-3. Photoresist spins speed curves for different resist viscosities showing how resist thickness varies as spin speed to the -1/2 power.

3. Post-Apply Bake

After coating, the resulting resist film will contain between 20 – 40% by weight solvent. The post-apply bake process, also called a softbake or a prebake, involves drying the photoresist after spin coat by removing this excess solvent. The main reason for reducing the solvent content is to stabilize the resist film. At room temperature, an unbaked photoresist film will lose solvent by evaporation, thus changing the properties of the film with time. By baking the resist, the majority of the solvent is removed and the film becomes stable at room temperature. There are four major effects of removing solvent from a photoresist film: (1) film thickness is reduced, (2) post-exposure bake and development properties are changed, (3) adhesion is improved, and (4) the film becomes less tacky and thus less susceptible to particulate contamination. Typical prebake processes leave between 3 and 8 percent residual solvent in the resist film, sufficiently small to keep the film stable during subsequent lithographic processing.

Unfortunately, there are other consequences of baking most photoresists. At temperatures greater than about 70°C the photosensitive component of a typical resist mixture, called the photoactive compound (PAC), may begin to decompose [1.3,1.4]. Also, the resin, another component of the resist, can crosslink and/or oxidize at elevated temperatures. Both of these effects are undesirable. Thus, one must search for the optimum prebake conditions that will maximize the benefits of solvent evaporation and minimize the detriments of resist decomposition. For chemically amplified resists, residual solvent can significantly influence diffusion and reaction properties during the post-exposure bake, necessitating careful control over the post-apply bake process. Fortunately, these modern resists do not suffer from significant decomposition of the photosensitive components during prebake.

There are several methods that can be used to bake photoresists. The most obvious method is an oven bake. Convection oven baking of conventional photoresists at 90°C for 30 minutes was typical during the 1970s and early 1980s. Although the use of convection ovens for the prebaking of photoresist was once quite common, currently the most popular bake method is the hot plate. The wafer is brought either into intimate vacuum contact with or close proximity to a hot, high-mass metal plate. Due to the high thermal conductivity of silicon, the photoresist is heated to near the hot plate temperature quickly (in about 5 seconds for hard contact, or about 20 seconds for proximity baking). The greatest advantage of this method is an order of magnitude decrease in the required bake time over convection ovens, to about one minute, and the improved uniformity of the bake. In general, proximity baking is preferred to reduce the possibility of particle generation caused by contact with the backside of the wafer.

When the wafer is removed from the hotplate, baking continues as long as the wafer is hot. The total bake process cannot be well controlled unless the cooling of the wafer is also well controlled. As a result, hotplate baking is always followed immediately by a chill plate operation, where the wafer is brought in contact or close proximity to a cool plate (kept at a temperature slightly below room temperature). After cooling, the wafer is ready for its lithographic exposure.

4. Alignment and Exposure

The basic principle behind the operation of a photoresist is the change in solubility of the resist in a developer upon exposure to light (or other types of exposing radiation). In the case of the standard diazonaphthoquinone positive photoresist, the photoactive compound (PAC), which is not soluble in the aqueous base developer, is converted to a carboxylic acid on exposure to UV light in the range of 350 - 450nm. The carboxylic acid product is very soluble in the basic developer. Thus, a spatial variation in light energy incident on the photoresist will cause a spatial variation in solubility of the resist in developer.

Contact and proximity lithography are the simplest methods of exposing a photoresist through a master pattern called a photomask (Figure 1-4). Contact lithography offers high resolution (down to about the wavelength of the radiation), but practical problems such as mask damage and resulting low yield make this process unusable in most production environments. Proximity printing reduces mask damage by keeping the mask a set distance above the wafer (e.g., 20 μm). Unfortunately, the resolution limit is increased to greater than 2 to 4 μm, making proximity printing insufficient for today’s technology. By far the most common method of exposure is projection printing.



Figure 1-4. Lithographic printing in semiconductor manufacturing has evolved from contact printing (in the early 1960s) to projection printing (from the mid 1970s to today).



Projection lithography derives its name from the fact that an image of the mask is projected onto the wafer. Projection lithography became a viable alternative to contact/proximity printing in the mid 1970s when the advent of computer-aided lens design and improved optical materials allowed the production of lens elements of sufficient quality to meet the requirements of the semiconductor industry. In fact, these lenses have become so perfect that lens defects, called aberrations, play only a small role in determining the quality of the image. Such an optical system is said to be diffraction-limited, since it is diffraction effects and not lens aberrations which, for the most part, determine the shape of the image.

There are two major classes of projection lithography tools – scanning and step-and-repeat systems. Scanning projection printing, pioneered by the Perkin-Elmer company [1.5], employs reflective optics (i.e., mirrors rather than lenses) to project a slit of light from the mask onto the wafer as the mask and wafer are moved simultaneously by the slit. Exposure dose is determined by the intensity of the light, the slit width, and the speed at which the wafer is scanned. These early scanning systems, which use polychromatic light from a mercury arc lamp, are 1:1, i.e., the mask and image sizes are equal. Step-and-repeat cameras (called steppers for short) expose the wafer one rectangular section (called the image field) at a time and can be 1:1 or reduction. These systems employ refractive optics (i.e., lenses) and are usually quasi-monochromatic. Both types of systems (Figure 1-5) are capable of high-resolution imaging, although reduction imaging is required for the highest resolutions.

Scanners replaced proximity printing by the mid-seventies for device geometries below 4 to 5 μm. By the early 1980s, steppers began to dominate as device designs pushed below 2 μm. Steppers have continued to dominate lithographic patterning throughout the 1990s as minimum feature sizes reached the 250nm levels. However, by the early 1990s a hybrid step-and-scan approach was introduced by SVG Lithography, the successor to Perkin-Elmer. The step-and-scan approach uses a fraction of a normal stepper field (for example, 25mm x 8mm), then scans this field in one direction to expose the entire 4 x reduction mask. The wafer is then stepped to a new location and the scan is repeated. The smaller imaging field simplifies the design and manufacture of the lens, but at the expense of a more complicated reticle and wafer stage. Step-and-scan technology is the technology of choice today for below 250nm manufacturing.
 


Figure 1-5. Scanners and steppers use different techniques for exposing a large wafer with a small image field.



Resolution, the smallest feature that can be printed with adequate control, has two basic limits: the smallest image that can be projected onto the wafer, and the resolving capability of the photoresist to make use of that image. From the projection imaging side, resolution is determined by the wavelength of the imaging light (λ) and the numerical aperture (NA) of the projection lens according to the Rayleigh criterion:





Lithography systems have progressed from blue wavelengths (436nm) to UV (365nm) to deep-UV (248nm) to today’s mainstream high resolution wavelength of 193nm. In the meantime, projection tool numerical apertures have risen from 0.16 for the first scanners to amazingly high 0.93 NA systems today producing features well under 100nm in size.


Before the exposure of the photoresist with an image of the mask can begin, this image must be aligned with the previously defined patterns on the wafer. This alignment, and the resulting overlay of the two or more lithographic patterns, is critical since tighter overlay control means circuit features can be packed closer together. Closer packing of devices through better alignment and overlay is nearly as critical as smaller devices through higher resolution in the drive towards more functionality per chip.


Another important aspect of photoresist exposure is the standing wave effect. Monochromatic light, when projected onto a wafer, strikes the photoresist surface over a range of angles, approximating plane waves. This light travels down through the photoresist and, if the substrate is reflective, is reflected back up through the resist. The incoming and reflected light interfere to form a standing wave pattern of high and low light intensity at different depths in the photoresist. This pattern is replicated in the photoresist, causing ridges in the sidewalls of the resist feature as seen in Figure 1-6. As pattern dimensions become smaller, these ridges can significantly affect the quality of the feature. The interference that causes standing waves also results in a phenomenon called swing curves, the sinusoidal variation in linewidth with changing resist thickness. These detrimental effects are best cured by coating the substrate with a thin absorbing layer called a bottom antireflective coating (BARC) that can reduce the reflectivity seen by the photoresist to less than 1 percent.
 


Figure 1-6. Photoresist pattern on a silicon substrate showing prominent standing waves.

 

 5. Post-Exposure Bake


One method of reducing the standing wave effect is called the post-exposure bake (PEB) [1.6]. Although there is still some debate as to the mechanism, it is believed that the high temperatures used (100°C – 130°C) cause diffusion of the photoactive compound, thus smoothing out the standing wave ridges (Figure 1-7). It is important to note that the detrimental effects of high temperatures on photoresist discussed concerning prebaking also apply to the PEB. Thus, it becomes very important to optimize the bake conditions. It has also been observed that the rate of diffusion of the PAC is dependent on the prebake conditions [1.7]. It is thought that the presence of solvent enhances diffusion during a PEB. Thus, a low temperature prebake results in greater diffusion for a given PEB temperature.


For a conventional resist, the main importance of the PEB is diffusion to remove standing waves. For another class of photoresists, called chemically amplified resists, the PEB is an essential part of the chemical reactions that create a solubility differential between exposed and unexposed parts of the resist. For these resists, exposure generates a small amount of a strong acid that does not itself change the solubility of the resist. During the post-exposure bake, this photogenerated acid catalyzes a reaction that changes the solubility of the polymer resin in the resist. Control of the PEB is extremely critical for chemically amplified resists.



(a)                                     (b)                                (c)


Figure 1-7. Diffusion during a post-exposure bake is often used to reduce standing waves. Photoresist profile simulations as a function of the PEB diffusion length: (a) 20nm, (b) 40nm, and (c) 60nm.

 6. Development


Once exposed, the photoresist must be developed. Most commonly used photoresists use aqueous bases as developers. In particular, tetramethyl ammonium hydroxide (TMAH) is used in concentrations of 0.2 - 0.26 N. Development is undoubtedly one of the most critical steps in the photoresist process. The characteristics of the resist-developer interactions determine to a large extent the shape of the photoresist profile and, more importantly, the linewidth control.


The method of applying developer to the photoresist is important in controlling the development uniformity and process latitude. In the past, batch development was the predominant development technique. A boat of some 10-20 wafers or more are developed simultaneously in a large beaker, usually with some form of agitation. With the push towards in-line processing, however, other methods have become prevalent. During spin development wafers are spun, using equipment similar to that used for spin coating, and developer is poured onto the rotating wafer. The wafer is also rinsed and dried while still spinning. Spray development has been shown to have good results using developers specifically formulated for this dispense method. Using a process identical to spin development, the developer is sprayed, rather than poured, on the wafer by using a nozzle that produces a fine mist of developer over the wafer (Figure 1-8). This technique reduces developer usage and gives more uniform developer coverage. Another in-line development strategy is called puddle development. Again using developers specifically formulated for this process, the developer is poured onto a stationary wafer that is then allowed to sit motionless for the duration of the development time. The wafer is then spin rinsed and dried. Note that all three in-line processes can be performed in the same piece of equipment with only minor modifications, and combinations of these techniques are frequently used.
 
 


Figure 1-8. Different developer application techniques are commonly used.

 7. Postbake


The postbake (not to be confused with the post-exposure bake that comes before development) is used to harden the final resist image so that it will withstand the harsh environments of implantation or etching. The high temperatures used (120°C - 150°C) crosslink the resin polymer in the photoresist, thus making the image more thermally stable. If the temperature used is too high, the resist will flow causing degradation of the image. The temperature at which flow begins is related to the glass transition temperature and is a measure of the thermal stability of the resist. In addition to cross-linking, the postbake can remove residual solvent, water, and gasses and will usually improve adhesion of the resist to the substrate.


Other methods have been proposed to harden a photoresist image. Exposure to high intensity deep-UV light crosslinks the resin at the surface of the resist forming a tough skin around the pattern [1.8]. Deep-UV hardened photoresist can withstand temperatures in excess of 200°C without dimensional deformation. Although it is commonly thought that the deep-UV radiation causes the crosslinking reaction directly, there is some evidence to suggest that ozone generated by the interaction of the light with atmospheric oxygen may cause (or enhance) the crosslinking reaction [1.9, 1.10]. Plasma treatments and electron beam bombardment have also been shown to effectively harden photoresist. Commercial deep-UV hardening systems are now available and are widely used.

8. Pattern Transfer


After the small patterns have been lithographically printed in photoresist, these patterns must be transferred into the substrate. There are three basic pattern transfer approaches: subtractive transfer (etching), additive transfer (selective deposition), and impurity doping (ion implantation). Etching is the most common pattern transfer approach. A uniform layer of the material to be patterned is deposited on the substrate. Lithography is then performed such that the areas to be etched are left unprotected (uncovered) by the photoresist. Etching is performed either using wet chemicals such as acids, or more commonly in a dry plasma environment. The photoresist “resists” the etching and protects the material covered by the resist. When the etching is complete, the resist is stripped leaving the desired pattern etched into the deposited layer. Additive processes are used whenever workable etching processes are not available, for example for copper interconnects. Here, the lithographic pattern is used to open areas where the new layer is to be grown (by electroplating, in the case of copper). Stripping of the resist then leaves the new material in a negative version of the patterned photoresist. Finally, doping involves the addition of controlled amounts of contaminants that change the conductive properties of a semiconductor. Ion implantation uses a beam of dopant ions accelerated at the photoresist-patterned substrate. The resist blocks the ions, but the areas uncovered by resists are embedded with ions, creating the selectively doped regions that make up the electrical heart of the transistors.
9. Strip


After the imaged wafer has been processed (e.g., etched, ion implanted, etc.) the remaining photoresist must be removed. There are two classes of resist stripping techniques: wet stripping using organic or inorganic solutions, and dry (plasma) stripping. A simple example of an organic stripper is acetone. Although commonly used in laboratory environments, acetone tends to leave residues on the wafer (scumming) and is thus unacceptable for semiconductor processing. Most commercial organic strippers are phenol-based and are somewhat better at avoiding scum formation. However, the most common wet strippers for positive photoresists are inorganic acid-based systems used at elevated temperatures.


Wet stripping has several inherent problems. Although the proper choice of strippers for various applications can usually eliminate gross scumming, it is almost impossible to remove the final monolayer of photoresist from the wafer by wet chemical means. It is often necessary to follow a wet strip by a plasma descum to completely clean the wafer of resist residues [1.11]. Also, photoresist which has undergone extensive hardening (e.g., deep-UV hardening) and been subjected to harsh processing conditions (e.g., high energy ion implantation) can be almost impossible to strip chemically. For these reasons, plasma stripping has become the standard in semiconductor processing. An oxygen plasma is highly reactive towards organic polymers but leaves most inorganic materials (such as are found under the photoresist) untouched.





Reference: www.lithoguru.com

Litho based Routing

 

Litho based routing can be understand from the below Dig, It is implemented below 28nm:
An automated flow has been implemented to detect printability hotspots using a model-based solution, and to automatically fix these hotspots during final routing optimization. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. Since the semiconductor industry is currently limited to 193nm scanners, no relief is expected from the equipment side and must come from the design side. Rule-driven routers fail to capture hotspots, as they are based on ideal polygons that do not represent the real silicon image. Model-based hotspot detection can validate design manufacturability and will account for complex two-dimensional effects that stem from aggressive scaling of 193nm lithography. To enable this solution, manufacturing teams started to release model-based lithography checks; initially as a service using the manufacturing flow to check small cells, and now by releasing process information to designers for full-chip lithography hotspot detection. However, if manual fixing is manageable at the cell level, hotspot removal in large placed and routed blocks or even full chip is more challenging. Not only is full-chip litho/etch simulation required to have a reasonable runtime, but the fixing solution needs to be connectivity-aware and incremental with a very fine step size. This is required for a timing-aware solution that mitigates hotspots without adversely affecting timing closure. The automated flow links a hotspot detection solution and a chip routing optimization tool. The hotspot detection solution passes the hotspot locations and associated fixing guidelines to the chip routing optimization tool. The chip routing optimization tool removes the hotspots in an incremental fashion so as to have no significant impact on timing, but a significant impact on printability. This process of checking for hotspots and incrementally fixing them is iterated until a hotspot-free design is achieved. This paper describes how fabless designers have integrated this hotspot detection solution in their design flow and how the hotspot removal flow efficiently removed most hotspots in real designs, thereby providing DFM closure.

It Provides capabilities at implementation phase to prevent ,detect and fix lithography issues. In this process we need to have technology files and flow options to have litho friendly vias, shielding and U-shapes litho aware routing. It does a pattern matching hot spot detection on the P&R database and does a Hot spot repair.
  

It can be defined as:

  1. Provide litho checks at sign off phase
  2. Pattern matching hot spot detection
  3. OPC and litho simulation
  4. Auto-correction rate calculation 







 Prob and sol:


After repair