Clock skews (timing skew)

Clock signal in synchronous circuits arrives at different components at different times.

Clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Reasons for the Skew:

Wire-interconnect length
Temperature variations
Variation in intermediate devices
Capacitive coupling
Material imperfections

Two Types of Clock Skew:

Negative skew
Positive skew

Positive skew:

Occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Negative skew:

Is the opposite:- the receiving register gets the clock earlier than the sending register.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Notes:
Less clock latency:
Lesser number of clock buf/inv
Less power consumption
Less Area