DC TOPO Synthesis

Recently I came up with a design which was very -very timing critical, then we took the design into  DC-Topo mode and used the ICC written out def and we got excellent improvement in the timing QOR

Design Compiler in topographical mode supports high-level physical constraints such as die area, core area and shape, port locations, cell locations and orientations, keepout margins, placement blockages, preroutes, bounds, vias, tracks, voltage areas, and wiring keepouts. Using floorplan physical constraints in topographical mode improves timing correlation with post-place-and-route tools, such as IC Compiler, by considering floorplanning information during optimization. You provide floorplan physical constraints to Design Compiler topographical mode using one of the following methods: Export the floorplan information in DEF files or a Tcl script from IC Compiler and import this information into Design Compiler Create the constraints manually You can examine most of these objects visually in your floorplan by using the Design Vision layout window. For more information about using the GUI to view physical constraints, see the “Viewing the Floorplan” topic in Design Vision Help.

Importing Floorplan Information

The main reason to use floorplan constraints in topographical mode is to accurately represent the placement area and improve timing correlation with the post-place-and-route design. You can provide high-level physical constraints that determine core area and shape, port location, macro location and orientation, voltage areas, placement blockages, and placement bounds. These physical constraints can be derived from IC Compiler floorplan data, extracted from an existing Design Exchange Format (DEF) file, or created manually.

You can import floorplan information into the Design Compiler tool by using one of the following methods:

Using DEF Files

To provide floorplan physical constraints in DEF files to the Design Compiler tool, you export the floorplan information from the IC Compiler tool by using the write_def command and import this information into the Design Compiler tool by using theextract_physical_constraints command. For more information, see the following topics:

Using a Tcl Script

Export the floorplan information from IC Compiler by using the write_floorplan command and import this information into the Design Compiler tool by using the extract_physical_constraints command

Physical Constraints Imported in the DEF File

1. Die Area
2. Placement Area
3. Macro Location and Orientation
4. Hard, Soft, and Partial Placement Blockages
5. Wiring Keepouts
6. Placement Bounds
7. Port Location
8. Preroutes
9. Site Array Information
10. Vias
11. Routing Tracks
12. Keepout Margins

Reference: https://solvnet.synopsys.com/