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the code you posted is i think incorrect..... correct one should be like thismodule ff( input clk, input rst, input a, output reg t1, output reg t2, output reg t3 );always @(posedge clk)beginif(rst)begint1=0;t2=0;t3=0;endelsebegint1=t2;t2=t3;t3=a;endendendmodule
your code is an active low reset FF and that is correct, but I have designed a FF without resetKindly visit the following to see with the reset FFhttp://mantravlsi.blogspot.com/2014/08/flip-flop-with-asynchronous-reset.html
the code you posted is i think incorrect..... correct one should be like this
ReplyDeletemodule ff(
input clk,
input rst,
input a,
output reg t1,
output reg t2,
output reg t3
);
always @(posedge clk)
begin
if(rst)
begin
t1=0;
t2=0;
t3=0;
end
else
begin
t1=t2;
t2=t3;
t3=a;
end
end
endmodule
your code is an active low reset FF and that is correct, but I have designed a FF without reset
DeleteKindly visit the following to see with the reset FF
http://mantravlsi.blogspot.com/2014/08/flip-flop-with-asynchronous-reset.html