Physical Design Interview Question

Filler cells are added ___.

a. Before Placement of std cells b. After Placement of Std Cells

c. Before Floor planning d. Before Detail Routing

If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2 b. Metal3 and metal4

c. Metal4 and metal5 d. Metal6 and metal7

What problem are you trying to solve by meeting “metal fill” design rules?

a. stress b. setup and hold violations

c. transition d. Density

Why does PnR tool require logical libraries in addition to physical libraries?Circle the one which is not part of the group.

a. Filler cell b. End Cap cell

c. Tap cell d. Jtag cell

Abstract view of the cell contains

a. Timing Information b. Power information

c. All metal layer information d. cell/pin name, size, blockage information

The delay is a function of the …… and ………. of the cell

a. input transition time, output load b. input load, output transition time

c. input setup time, output load d. input transition time, output fanout

In general standard practice is to start the floor plan with ….% of utilization.

a. 60 b. 70

c. 80 d. 90

High utilization can

a. cause routing congestion b.close timing easily

c. decrease DRC violations d. All of the above

The height and width of the unit tile is defined in

a. timing library b. reference library

c. technology file d. physical library

Standard cells are placed in regular fashion based on

a. cell rows b.macros

c. blockage d. all of the above

height of the all cell rows are common and is equal to

a. techmology node b. unit tile

c. highest cell height d. lowest cell height

If pad area is more than core area then it is

a. pad limited b.core limited

c. chip limitd d. die limited

In staggered bonding bond pads are of ….. height

a. same b. different

c. dual d. all of the above

To fill that gap and to provide I/O pad power ring connectivity ……. are used

a. corner cells b. core filler cells

c. tap cells d. end cap cells

Filler cells have timing arcs.

a. true b. false

c. partially true d.

Fillers cells are used for

a. continuity of well and power b. to fill the gap

c. continuity of standard cells d. to avoid IR drop issues

Typically, hard macros are placed near the ….. of the core area

a. centre b. sides

c. diagonal d. other macros

Connectivity of the macros can be analysed using

a. placement of macros b. congestion

c. fly lines d. manual effort

partial blockages block

a. all standard cells except buffers and inverters to be placed. b. all standard cells except buffers to be placed.

c. all standard cells except clock buffers to be placed. d. all standard cells with certain percentage

SAIF means

a. Switching Action Interchange Format b. Switching Activity Interchange Format

c. Switching Activity Interaction Format d. Standard Activity Interchange Format

Power mesh structure include

a. ring, strap, rail b. pad, I/Os, ring

c. strap, rail, I/O pads d. ring, strap, rail, standard cells

Spare cells doesn’t connect to any functional logic and are not functionally used.

a. true b. false

c. partially correct d. none of the above

JTAG cells are generally placed near……...

a. sides b.I/O ports

c. centre d. corner

Scan chains are formed in alphanumeric order in synthesis without any actual placement information

a. true b. false

c. d.

Legality checker algorithm checks for ……. placed cells

a. illegally b. legally

c. outside d. inside

Hold timing is analyzed only after the …..

a. place b. CTS

c. route d. floorplan

wire tracks assigned for particular metal in …….

a. vertical routing direction b. horizontal routing direction

c. non-prefered routing direction d. preferred routing directions

Via reliability can be improved by adding …………..

a. single via b. multiple via

c. double vias d. via

Metal fill step is required to

a. have same density b. have different density

c. increase yield d. meet timing

SAIF is preferred over user-defined toggle rates for accurate leakage power optimization

a. true b. false

c. partially true d. None

The SCANDEF file contains the scan ordering information which will be maintained during placement

a. true b. fale

c. partially true d.

Antenna file provided by the foundry has

a. antenna length b. antenna ratio

c. antenna area d. antenna charge density

Finding Manhattan distance is known as

a. virtual route b. global route

c. detail route d. track route

Finding Manhattan distance by assigning to metal layers is known as

a. virtual route b. global route

c. detail route d. track route

Normal buffers can be used in clock tree if timing is met

a. true b. false

c. not always true d. partially true

Which of the following is not present in SDC ___?

a. max trans b. max cap

c. max fanout d. max current density

Order in Sequence

a. translate b. optimize

c. mapping d. incremental synthesis

When stated as 0.13μm CMOS technology, what does 0.13 represent?

a. gate length b. gate width

c. technology node d. CMOS size

What kinds of timing violations are in a typical timing analysis report?

a. setup, hold violations b. slack

c. none of the above d. all of the above

Hard macros are in the form of …. ?

a. Netlist b. GDS

c. LIB d. DEF

RTL stands for ?

a. Register Transfer Level b. Register Transfer Logic

c. Random Technique Logic d. Required Timing Logic

Worst case corner means?

a. slow process, highest voltage and highest temperature b. fast process, lowest voltage and lowest temperature

c. nominal process, lowest voltage and highest temperature d. slow process, lowest voltage and highest temperature

Best case corner means?

a. fast process, highest voltage and highest temperature b. fast process, highest voltage and lowest temperature

c. slow process, highest voltage and lowest temperature d. fast process, lowest voltage and lowest temperature

WLM is based on the statistical estimates of R and C based on ?

a. Net Fan-out b. R per unit length

c. C per unit length d. Statistical estimation

Choose not part of the group?

a. top b. segmented

c. enclosed d. ports

During elaboration which of the below tasks are performed?

a. Builds data structures

b. Infers registers in the design

c. Performs higher-level HDL optimization, such as dead code removal

d. All of the above

Synthesis means

a. Conversion of RTL to Netlist b. Conversion of Netlist to RTL

c. Conversion of RTL to GDS d. Conversion of RTL to DEF

What are the advantages of clock gating?

a. Increase clock frequency b. save clock power

c. save leakage power d. save area

Which one of the below is not a semiconductor process node?

a. 90 b. 65

c. 55 d. 45

IP core types doesn’t include:

a. Soft core b. Hard core

c. Firm core d. Chip core

Hard cores are in the form of

a. RTL b. Netlist

c. GDS d. DEF

ASICs have less unit cost, higher speed, low power. True or Flase?

a. True b. False

c. Can’t say d. Partially true

Which is non-synthesizable here?

a. Event b. Event trigger

c. posedge d. negedge

Mutiple if statements with multiple branches ewsult in

a. Priority encoder b. priority decoder

c. multiplexer d. Register

A proper conditional assignment will infer..

a. mux b. flip flop

c. xor d. encoder

always @(posedge clk) begin

reg1 <= in0;

reg2 <= reg1;

reg3 <= reg2;

end

What hardware is infered with above code?

a. 1 flop b. 2 flop

c. 3 flop d. 4 flop

always @(posedge clk) begin

reg1 = in0;

reg2 = reg1;

reg3 = reg2;

end

What hardware is infered with above code?

a. 1 flop b. 2 flop

c. 3 flop d. 4 flop

Which one of the below inefficient RTL coding causes latches:

a. Incomplete if-else statement b. Incomplete case statement

c. missing default in case statement d. all of the above

Technology libraries are provided by

a. EDA vendor b. Fab house

c. Freely avaialble d. We create libraries

.lib file doesn’t consists of

a. Logic cells of varied drive strength, inpus b. Cells such as AOI, OAI, flip-flops

c. Geometrical information of metal layers d. All of the above

synthesis strategies include

a. Top down b. Bottom up

c. heirarchical d. All the above

What are the constraints you used for the synthesis?

a. Timing b. Area, Power

c. Logical DRC d. All of the above

What will happen to a design that is synthesized without any constraints?

a. Wont synthesize b. Timing won’t meet

c. Will synthesize properly d. Won’t optmize

Translate-Optimize-Map is nothing but ..?

a. DFT b. Physical Design

c. Synthesis d. RTL Design

Logic library has

a. Timing, Area, Power b. Operating Conditions

c. Wire Load Models d. All the above

units used for time, capacitance, power, voltage, current etc are specified in

a. .lib b. spef

c. .tf d. .def

Process variation accounts for

a. Deviation in semiconductor fabrication process b. Deviation in synthesis

c. Deviation in DFT d. Deviation in Physical Design

The voltage drop is due to …….. resistance in the supply wires

a. nonzero b. zero

c. Infinite d. None of the above

The propagation delay ………… with increased temperature

a. Increases b. Decreases

c. Remains same d. Vanishes

How to improve synthesis optimization results?

a. Create path groups b. Fix heavily loaded nets

c. Ungroup hierarchies on the critical path d. All of the above

Disadvantage of bottom-up synthesis aproach is

a. Multiple iterations required until the interfaces are stable b. Synthesizes large designs by using the divide-and-conquer approach

c. Requires less memory than top-down synthesis d. Allows time budgeting

In top-down synthesis approach

a. Only top level design is synthesized b. Subdesigns are synthesized seperately

c. top level and subdesigns are synthesized seperately d. top-level design and all its subdesigns are synthesized together

Constraints are generally written in …….. format

a. TCL b. PERL

c. SDC d. TEXT

Linking is the process of

a. Resolving references b. Unresolving references

c. Mapping to technology library d. Synthesizing the design

‘Analyze’ checks for

a. Semantics b. RTL

c. Netlist d. IP

by default, the tool assumes that the external load on the ports is

a. Finite b. Infinite

c. Zero d. None

By default, tool assumes ……….. drive strength on input ports.

a. Finite b. Infinite

c. Zero d. None

WLM is based on

a. Net length and R and C b. Designers requirements of design

c. Some estimation of R and C given by fab house d. statistical estimates of R and C based on “Net Fan-out”.

Enclosed wire load model

a. Uses the wire load model specified for the top level of the design hierarchy for all nets in a design and its sub designs. b. Uses wire load model of the smallest design that fully encloses the net is applied.

c. For each net segment crossing heirarchy, the wire load model of the design containing the segment is used d. none

Setup violations can be fixed by

a. slowing down the clock b. increasing drive strength

c. adding buffers d. All of the above

Hold violations can be fixed by

a. increasing the delay of the data path b. decreasing the clock uncertainty(skew

c. Adding buffers d. All of the above

DRC constraints exists in

a. SDC b. Library

c. Design d. None

external drive strength of input port can be specified using SDC

a. set_driving_cell b. set_drive

c. set_load d. set_max_fanout

Estimated clock insertion delay is modeled using this constraint

a. set_clock_latency b. set_clock_uncertainty

c. set_clock_transition d. set_clock_gating_check

Which is having highest precedence?

a. Timing constraints b. area constraints

c. power constraints d. all are of highest precedence

Synthesis tool performs area optimization only on those paths that have…………….

a. positive slack b. negative slack

c. worst negative slack d. total negative slack

Grouping of timing paths allows

a. Control the optimization of design b. Optimize near-critical paths

c. Optimize all paths d. all of the above

Following methods can be employed to improve the timing of the design

a. Create path groups

b. Fix heavily loaded nets

c. Ungroup hierarchies on the critical path

d. all of the above

Disadvantage of bottom-up synthesis strategy is

a. Synthesizes large designs by using the divide-and-conquer approach

b. Requires less memory than top-down synthesis

c. Allows time budgeting

d. Multiple iterations required until the interfaces are stable

In bottom-up strategy individual subdesigns are synthesized ………

a. seperately b. together

c. one by one d. regularly

In top down synthesis strategy the top-level design and all its subdesigns are synthesized …..

a. seperately b. together

c. one by one d. regularly

Architectural optimizations are carried out over

a. mapped dedign b. unmapped design

c. maped netlist d. unmapped netlist

The elaborate command automatically elaborates the top-level design and all of its ….

a. references b. subdesigns

c. instances d. all of the above

At the end of elaboration, RTL Compiler displays any …… references

a. resolved b. connected

c. unresolved d. unconnected

In test mode, all FFs are configured as a---------?

a. Serial shift register b. Parellel shift register

c. Serial Counter d. Ring counter

Fault coverage is defined as ?

a. The ratio of No. of detected faults to total no. of faults b. The ratio of No. of faults to total no. of detected faults

c. The ratio of No. of detected faults to (total no. of faults –no. of undetectable faults) d. The ratio of no. of undetectable faults to (total no. of faults – No. of detected faults)

Stuck at 0 modeling represents?

a. Signal is permanently low b. Signal is permanently high

c. Signal is either high or low d. Signal is neither high or low

In DFT which one of the below Controllability and which one is observability?

a. you can drive it to a specified logic value by setting the primary inputs to specific values b. you can predict the response on it and propagate the fault effect to the primary outputs, where you can measure the response.

c. You can scan the values from primary input to primary output

d.

STA Checks …….. delay requirements of the circuit without any input or output vectors.

a. library b. dynamic

c. timing d. static

Circle the incorrect one

a. Dynamic Timing Analysis (DTA) and Static Timing Analysis (STA) are not alternatives to each other

b. Can’t run on asynchronous deigns and hence Dynamic Timing Analysis (DTA) is the best way to analyze asynchronous designs

c. Runs faster and hence lesser analysis time

d. verifies functionality of the design by applying input vectors and checking for correct output vectors

Circle the incorrect one

a. Takes lot of time simulate and verify

b. best suitable for designs having clocks crossing multiple domains

c. can be used for synchronous as well as asynchronous designs

d. Checks static delay requirements of the circuit without any input or output vectors.

…………. can be used for synchronous as well as asynchronous designs

a. static timing analysis b. dynamic timing analysis

c. spice timing analysis d. simulation timing analysis

Device level timing analysis is carried out using …….. simulation

a. Verilog b. SPICE

c. Dynamic d. Timing

All paths in the design may not run always in worst case delay. Hence the analysis is ……..

a. pessimistic b. optimistic

c. complete d. incomplete

STA …………. for logical correctness of the design

a. does check b. does not check

c. partially check d. None of the above

STA is not suitable for ………….circuits

a. synchronous b. pseudo-synchonous

c. asynchronous d. digital

Gate delay =function of …………………

a. (input load , output transition). b. (input transition time, input load).

c. (input transition time, output transition) d. (input transition time, Cload).

Cell or gate delay is calculated using …………

a. LIB b. LEF

c. NLDM d. DEF

NLDM is highly accurate as it is derived from …………. characterizations

a. SPICE b. CCS

c. CMOS d. LIB

Wire delay = function of …………….

a. (Rnet, Cnet+Cpin) b. (Cnet, Rnet+Cpin)

c. (Rnet, Cnet+Rpin) d. (Rnet, Cload+Cpin)

As per Elmore delay model, doubling the length of the wire ………… its delay

a. Doubles b. quadruples

c. Halves d. multiples

Learn More ==>
Physical design part1
Physical design part2
Physical design part3
Placement

verilog interview question part1
verilog interview question part2
verilog interview question part3