Wafer related definitions: Wafer sawing

Wafer sawing

 

Wafer sawing is the last back-end operation in which a processing error can convert an entire $50,000 wafer into thousands of pieces of expensive scrap. Proper dicing of wafers requires experience, judgement, and high-performance equipment. Successful sawing requires selecting the correct saw blade from dozens of possibilities and finding the proper combination among dozens of control settings. Wafer thickness and composition, the width of the saw streets, and the desired die size must be considered when selecting sawing parameters. The wrong blade or the wrong combination of parameters can ruin the wafer.

The continuing shrinkage of semiconductor devices toward smaller feature size and higher density is raising the hurdle of sawing. Wafers are designed to hold as many die as possible. Producing a wafer is a fixed cost, so more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow “streets,” which are the cut lines for singulating the die. The narrower the streets, the more die – and the more challenging the sawing.

While several new singulation technologies are being developed or in limited use, ordinary silicon wafers, which comprise more than 90% of wafer volume, are sawn with a diamond saw blade. Selecting the proper saw, diamond blade, and mounting tape are three keys to success.
Dicing Saws

Silicon dicing saws offer a wide variety of models with many options. Options include manual or fully automated operation; single-blade or multi-blade cutting; cutting in one direction only or bi-directional; blade mounting on a 2- or 4-in.-diameter hub; cooling water flow from a single jet or from multiple jets; and spindle rotational speeds ranging from 1,000 to 60,000 rpm.

Figure 1 shows an operating saw, showing the rotating saw blade and the spray of cooling water.

Figure 1. Close-up of an operating saw, with cooling water spraying at the top of the rotating blade and the wafer. Photo courtesy of Disco.Click here to enlarge image

Post-saw cleaners, which remove the residual silicon dust, may be a part of the saw or standalone equipment. Automatic blade “dressing,” to maintain the cutting surface, may be included in the saw.

A semiconductor manufacturer may routinely saw large quantities of wafers. Manufacturers have the advantage of a limited family of products and materials, however, so that they can standardize their sawing equipment and processes. As a wafer service provider, every month we must saw wafers with hundreds of different part types from any of 30 wafer manufacturers. We use two types of saws to deal with this variety: semiautomatic and fully automated machines.

The semiautomatic saw dices single wafer orders that have low to moderate sawing complexity. This saw has one cooling jet, a single blade on a 2-in. hub, and a maximum spindle speed of 40,000 rpm. The operator programs the saw and must monitor the sawing, intervening as needed.

In summary, wafer sawing remains both an art and a science. For best results, both high-performance equipment and the proper materials must be combined with expert human judgement and experience.

 

 

 

seal ring

  

1. A wafer edge seal ring structure comprising:

a substrate;

• a layer of polysilicon formed over said substrate having a circumferential recess thereat between about 1.6 to 2.0 Å from the edge of said substrate;
• a first interlevel dielectric layer deposited on said layer of polysilicon having a circumferential recess thereat between about 1.0 to 1.5 mm from the edge of said substrate;
• a first metal layer deposited on said first interlevel dielectric having a circumferential recess thereat between about 2.5 to 3.1 mm from the edge of said substrate;
• a second interlevel dielectric deposited on said first metal layer having a circumferential recess thereat between about 2.0 to 2.6 mm from the edge of said substrate;
• a second metal layer deposited on said second interlevel dielectric layer having a circumferential recess thereat between about 1.5 to 2.0 mm from the edge of said substrate;
• a third interlevel dielectric deposited on said second metal layer having a circumferential recess thereat between about 3.0 to 3.5 mm from the edge of said substrate;
• a third metal layer deposited on said third interlevel dielectric layer having a circumferential recess thereat between about 2.5 to 3.1 mm from the edge of said substrate; and
• a passivation layer deposited on said third metal layer.

2. The structure of claim 1, wherein said substrate is silicon.

3. The structure of claim 1, wherein said substrate contains semiconductor devices.

4. The structure of claim 1, wherein said first interlevel dielectric layer is BPTEOS.

5. The structure of claim 4, wherein said first BPTEOS layer has a thickness between about 9,000 to 10,000 Å.

6. The structure of claim 1, wherein said first metal layer is aluminum-copper.

7. The structure of claim 6, wherein said first metal layer has a thickness between about 5,000 to 5,600 Å.

8. The structure of claim 1, wherein said second interlevel dielectric layer is a sandwich dielectric structure.

9. The structure of claim 8, wherein said sandwich dielectric structure has a thickness between about 8,000 to 10,000 Å.

10. The structure of claim 1, wherein said second metal layer is aluminum-copper.

11. The structure of claim 10, wherein said second metal layer has a thickness between about 5,000 to 6,000 Å.

12. The structure of claim 1, wherein said third interlevel dielectric layer is SOG.

13. The structure of claim 12, wherein said third SOG layer has a thickness between about 8,000 to 10,000 Å.

14. The structure of claim 1, wherein said third metal layer is aluminum-copper.

15. The structure of claim 14, wherein said third metal layer has a thickness between about 8,000 to 8,200 Å.

16. The structure of claim 1, wherein said passivation layer is a photosensitive polyimide.

17. The structure of claim 16, wherein said polyimide has a thickness about 3.0 micrometers.