HFN ( High Fanout Net Synthesis )

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 Fanout:

Fanout is the number of gate inputs to which the output can be safely connected. i.e., The load that a gate output can drive. The maximum fanout of an output measures it's load-driving capability. Fanout belongs to the output.

High fanout net synthesis :

High Fanout Nets are the nets which drive more number of load. High fanout nets other than clocks are synthesized at the placement stage. In logic synthesis, high fanout nets like reset, scan enable etc are not synthesized. You should verify that the SDC used for PnR should not have any set_ideal_network or set_dont_touch commands on these signals. Also, make sure you set an appropriate fanout limit for your library using the command set_max_fanout.

set_max_fanout during synthesis this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net.

Generally at placement step HFNS performed. HFNS can also be performed at synthesis step using Design Compiler. But it's not good idea, Buffers will be removed during PD and again HFNS is performed. It's very time consuming process. So HFNS at synthesis step is not recommended. HFNS at synthesis step gives an idea whether HFN are present in data path or not. Generally HFN are present in clock paths, rest, enable  and scan paths. 

Care that should taken during HFNS:

1. Make sure an appropriate fanout limit is set using

set_max_fanout command

2. Verify the SDC used for PD should not have

set_ideal_network or set_dont_touch commands on High  Fanout Nets.

3. Use ideal clock network - As clock nets are synthesized separately during Clock Tree Synthesis (CTS) step, we set clock network as ideal network.