Wednesday, 7 October 2015

prime time flow: STA : Static timing analysis


Set search path
Set link .libs
Read ldb
Read verilog
Currenct design
Link design
Read constraints
Create clocks
I/O delays
Set uncertainty, source latency
Set clock trans
Set multy cycle path
Set false path
Set case analysis

update timing
Check timing



Read Paracitics
Check timing
Report global timing

2 comments:

  1. It needs to be clear ... This is confusing

    ReplyDelete
    Replies
    1. yes right. Elaboration of flow should be done

      Delete