Set search path
Set link .libs
Read ldb
Read verilog
Currenct design
Link design
Read constraints
Create clocks
I/O delays
Set uncertainty, source latency
Set clock trans
Set multy cycle path
Set false path
Set case analysis
update timing
Check timing
Read Paracitics
Check timing
Report global timing
It needs to be clear ... This is confusing
ReplyDeleteyes right. Elaboration of flow should be done
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