Physical Design Routing Process : VLSI chip metal routing

1. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. 
2. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. 
3. The connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. 
4. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. 
5. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. 
6. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.

 Routing create physical connections  to all the data signal if clock nets are already routed after clock tree optimization.

There are 3 stages in routing
(i)GLOBAL ROUTING
(ii)TRACK ASSIGNMENT
(iii)DETAIL ROUTING

Global Routing:

First the design is divided into small boxes every box is called global routing cells (gcells or buckets)

every gcell having the a number of horizontal routing resources and vertical routing resources.

global routing assigns nets(logical connectivity not metal connectivity) to spacific metal layers and global routing cells.

By using global routing we can analyze congestion.

Congestion =(required routing resources > available routing resources)

If any gcell have congestion then detouring(avoid the gcell routing through another gcell).

Track Assignments :

Assigns each net to the spacific tracks.

Nets are laydown the metal traces.

Traces=metal connectivity.

 

Detail Routing:

Detail route dones actual routing. means actual routing metal connections. it checks also physical drc's.

Detail routing does not work on the entire chip at the same time like track assignment, instead it works be rerouting within the confines of a small area called an "sbox".

sbox : divide the block into mini boxes these are used for the detail route.

Grid based and gridless routing:

 In grid based routing, a routing grid is superimposed on routing region. Routing takes place along the grid lines. The space between adjacent grid lines is called wire pitch and is equal to sum of minimum width of wires and spacing of wires. On the other hand, any model that does not follow grid based routing is termed as gridless routing model. This model is suitable for wire sizing and perturbation and is more complex and slower than grid based routing. In other words, grid based routing is much easier and simpler in implementation. We have discussed here routing in VLSI designs. Although many advanced tools are available for achieving the purpose, most of these compromise with the quality of results to save run-time. Almost all tools have the option of routing with more emphasis on meeting timing or congestion. With most of the tools, in present day multi-million gate designs, perfect DRC-free routing (without opens and shorts) is generally not obtained in first pass. You have to route incrementally a few times to achieve the same.