Clock tree consume 50-70% of the total power of the Design, Clock signal is the highest frequency toggling signal in any any chip, dynamic power is directly proportional to the switching frequency of the devices. This implies that clock path cells would contribute maximum to the dynamic power consumption in the Design.
Therefore clock gating techniques is used to turn off the clock when it is not needed. if you see the follwoing FF which is coming from a series of clock buffer, if this logic is not in a active mode then we can turn off the clock signal with an enable signal.
We can use an AND gate with enable signal to prevent this problem. whenever the enable is high then only it will send the clock signal to the clock tree and FF.
Why latch based clock gating is used?
The output of the AND gate feeding the entire clock path can give a glithy output, See the following figure:
if the enable will come at the clock edge then we dont see any glitch at the output of the and gate but we dont know when the enable signal will come so we can always have a possibility of glitch at the output of the AND gate. To prevent this we have to use a negative-edge triggered FF. This would ensure that the signal is changing after the fall edge of the CLOCK signal.
The second part in not clear why we go for latch based Clockgating.
ReplyDeleteWhat is discussed here is the Clockgating setup and hold check.
consider example of positive edge triggered flop. In this case we need to use negative level sensitive latch for gate enable signal. during positive level, latch will be in sleep mode and acts like glitch control. otherwise, it will propagate to flop clock pin. Another check we need to do here is that there should not be any combo logic (apart from buffer/inverter), because that will violate whole purpose of latch. if latch has single clock gate in fanout then icg (integrated clock gate - has or, latch,and cells integrated) cell gets used.
Deletefor ICG, 2 inputs go to OR cell (test and enable signals). OR output goes to latch d pin and latch output goes to AND cell. Both latch and clock gate get same clock input
Can you explian in more details?
ReplyDelete