set_input_delay ; set_output_delay

Consider your chip is going to be placed in a board.. and input comes from pre block(asume a chip) and your output goes to other chip..

Then if u operate all this three chips as same clock...

Then from the previous chip it takes time to reach your chip.. consider delay of i/o pads of previous chip and pcb delay...

If you dont give input delay then at rising clock edge your chip excepts data to be present but due to delay data will arrive late.. this leads to fault logic..

 

If u give delay then you chip makes some delay within it such that the data reaches the input register(not input pin) at next rising edge...and you logic works..

Similarly to output pin also so that next module prepare themselves..

- set input_delay : Specifies a timing delay from one group of points to another (maybe clock signal ).Define the timing arrival at Input port when clock comes .

- set_output_delay : signal must arrive at least the specified amount of time that define by command "set_output_delay" before the clock signal