what is the difference between clk buffer and normal buffer?
1. clk buffer having equal rise time and fall time and normal buffer not like that.2. Clock buffers are usually designed such that an input signal with 50% duty cycle produces an output with 50% duty cycle. This usually isn't true for a normal buffer.
3. clock buffers sometimes have input and output pins on higher metal layers to avoid the need for vias in the root clock distribution network. Normal buffers have pins on lower layer like metal.
4. Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some special property like high drive strength and less delay. Clock buffers have equal rise and fall time. This prevents duty cycle of clock signal from changing when it passes through a chain of clock buffers.
You could have explained with some Cmos structure about how they are having equal rise and fall time.
ReplyDeletewhat are the disadvantages of using clock buffers ??
ReplyDeletebigger area. you match pull down resistance and pull up resistance. NMOS resistance is lesser than pmos so you need stronger pmos transistors or put pmos in parallel to get same drive as pull down.
Deletewhat happens if the duty cycle of clock buffers is >50% and <50%.
ReplyDeleteWhen you connect a chain of buffers then you duty cycle furthur degrades and it is going to be a huge impact on clock and at some point of time clock signal cannot be recognized.
Deleteif it continues then clock signal wont be recognized at endpoint side
ReplyDelete