Why NAND structures are preferred over NOR ones?

Both NAND and NOR are classified as universal gates, but we see that NAND is preferred over NOR in CMOS logic structures. Let us discuss why it is so:


We know that when output is at logic 1, pull up structure for the output stage is on and it provides a path from VDD to output. Similarly, pull down structure provides a path from GND to output when output is logic 0. Pull up and pull down resistances are one of major factor in determining the speed of cell. The inverse of pull up and pull down resistances are called output high drive and output low drive of the cell respectively. In general, cells are designed to have similar drive strength of pull up and pull down structures to have comparable rise and fall time.



NMOS has half the resistance of an equal sized PMOS. let us say resistance of a given sized NMOS is R then resistance of PMOS of same size will be 2R. In NAND gate, two NMOS are connected in series and two PMOS are connected in parallel. So, pull up and pull down resistances will be:

Pull up resistance = 2R || 2R = R
Pull down resistance = R + R = 2R



On the other hand, in a NOR gate, two NMOS are connected in parallel and two PMOS are connected in series. The pull-up and pull-down resistances, now, will be:
Pull up resistance = 2R + 2R = 4R
Pull down resistance = R || R = R/2



NAND gate has better ratio of output high drive and output low drive as compared to NOR gate. Hence NAND gate is preferred over NOR.



To use NOR gate as universal gate either pull up or pull down structure has to be resized(decrease the length of PMOS cells or increase length of NMOS cells) to have similar resistance as resistance is directly proportional to length (length of channel here).

Context hier signoff

 Context: 

What is it?

Top-level context captures the actual timing information at the block boundary•

What does it contain?

• Input/output boundary conditions
• Non-SDC informationsuch as CRPR, AOCV, POCV, cross-block exceptions, SI and noise information, MIM pessimism reduction.
• Support for bounded context for MIM instances•
• 
  
• PrimeTimecan generate context using characterize_context/write_contextset_hier_config/write_hier_data
• There are 2 user interfaces to generate the context. 
• One is with characterize_context/write_contextfor blocks in netlists. 
• The other is set_hier_config/write_hier_datafor blocks in HyperScalemodels. 
• The context generated from both UI contains the same content.

Ref: solvnet

Verifying the Power Network Definition : check_mv_design

•  To verify the power network definition for a multivoltage design, run the check_mv_design command. 
• This command checks for various types of violations such as inconsistent and conflicting library settings, missing isolation cells, and incorrect voltage shifting across power domains. •
• To check the power and ground connections, use the -power_connectivity option.
•  When you use this option, the tool checks the power and ground connections in addition to the power network definition, and updates the connections if it finds any issues. By default, it does not check the power and ground connections. 
• To specify the maximum number of messages for each violation type, use the -max_message_count option. By default, it reports a only 20 occurrences of a given violation type

# Procedure in ICC Apply the UPF

 load_upf $upf_input_file_name

## Common command used in UPF 

• create_supply_port
• create_supply_net
• create_power_switch
• connect_supply_net
• create_power_domain
• set_isolation
• set_level_shifter
• set_retention
• add_port_state create_pst add_ast_state .. et

 commit_upf … … 

# create logical supply nets set_app_options -as_user_default \ -list {mv.pg.create_floating_pg true} connect_pg_net –automatic 

check_mv_design

CLP low power checks

 Once we start working on low power design, we need to perform low power checks 

That includes 

    Reading the PG netlist 

    Reading the UPF

    Run low power checks called CLP

Make sure IN ICC your check_mv_design is clean

Types of low  power checks

      Static Checks  

      Dynamic checks : Dynamic checks are performed on the design while running simulation. Dynamic checks detect behavioral issues in the design, such as incorrect power sequencing of power domains

Isolation cells

Lets look into the below picture , where we have two power domains PD1 & PD2. 

There is a signal crossing from PD1 to PD2.

When the chip is in functional working mode, when all the power domains are up -> 

Signal s1 will be  either a 0 or 1 value.

Now when the  PD_1 is powered-off and PD_2 is powered-ON.

    The value of signal s1 is unknown. That will corrupt the powered-up logic in the PD_2 domain

This is the condition where we need to insert isolation cells to avoid corrupting the signal S1. 

When we run CLP, tool will flag the below errors.

Clp-report-isolation-check

Level Shifter

Consider the scenario when  both of the power domains are powered-up. 

Now if voltage difference between the power domains is less than a threshold value, or means both the domains are working at equal voltage. then  there are no issues in the design. 

 if the voltage difference is greater than the threshold value, means PD3 is 1.5v & PD4 is 0.85, then a logic 1 at PD_1 can be assumed a logic 0 at PD_2. This leads to incorrect data transmission.

TO avoid this condition we need a level shifter cell. 

A level shifter cell can be of the following two types:

• High-to-Low – Converts a high-voltage level to a low-voltage level. It is inserted when the source power domain operates at a higher voltage and the sink power domain operates at a lower voltage.
• Low-to-High – Converts a low-voltage level to a high-voltage level. It is inserted when the source power domain operates at a lower voltage and the sink power domain operates at a higher voltage.

clp Level shifter checks: report

Retention cells  &    Checks

Consider you have a power domain, which is powered-down. When the domain is powered-up again, all the state information from before the domain was powered-down is lost. To avoid this, designers place retention cells in power domains, which stores the state value of the power domain. Retaining the state value helps the power domain become operational sooner.

A design may have multiple power domains that are powered-down, which may lead to many retention issues. The simulator runs various retention checks on the design to find out the retention issues, and flags an error in case of a violation.

Back-to-Back Checks

• Sometimes your design has back-to-back cells, which might be any of the following types:
• Isolation and level shifter cell
• Level shifter and isolation cell
• Isolation and isolation cell
• Level shifter and level shifter cell

Other checks

• The design cells have missing liberty attributes.
• The isolation, level shifter, or retention supply is powered-down during the active isolation, level shifting, or retention period.
• The power signal of a power domain gets corrupted.
• The input of a power domain toggles when the power domain is powered-down.
• The power state table or the supply port reaches an illegal or undefined state.

https://www.powerelectronictips.com

CLP retention cells checks

• A retention cell is required, but it is neither present in the design nor specified in the UPF file.
• A retention cell is not required (as the power domain is an always-on domain), but it is either present in the design or specified in the UPF file.
• A retention cell is present in the design, but it does not have the corresponding strategy defined in the UPF file.
• A retention strategy is specified in the UPF file, but a retention cell is not present in the design.
• The retention condition is not asserted when the power domain is powered-down.
• The retention control signal is not generated from an always-on domain, or is unconnected, or is driven by a constant.
• The retention condition is disabled at power down or power up.
• The retention condition toggles at power down.

Retention cells

These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.

 All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/place/route them. 

In a nut-shell, “When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”.

The retention flop has the same structure as a standard master-slave flop. 

However, the retention flop has a balloon latch that is connected to true-Vdd. 

With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch.

 Similarly, when the block comes out of sleep, the data can be written back into the flip-flop

CLP Static checks

• Static checks detect architectural issues in the design.
• As a missing isolation or level shifter cell.
• Can be performed without running a simulation
• Save time and effort as you do not need to write a testbench. So you can run them on your low-power design as soon as the design is readyThere are two kinds of static checks: static RTL and static gate-level simulation (GLS) checks. The static RTL checks are run on RTL designs and static GLS checks on gate-level design

Level Shifter Cells

Level Shifters (LS) are special standard cells used in Multi Voltage designs to covert one voltage level to another. 

As Multi Voltage designs have more than one voltage domain, level shifters are used for all the signals crossing from one voltage domain to another voltage domain. 

Like isolation cells, level shifters are inserted by the synthesis tool

Low to High Level Shifters

Low to High LS are used for signals crossing from a lower voltage domain to higher voltage domain.

It basically amplifies the source signal so that it can be interpreted properly in the destination domain. 

Suppose a 0.7V signal is crossing from 0.7V voltage domain to 1.0V voltage domain. Now in the lower voltage domain it corresponds to logic-1 but in higher voltage domain it is neither logic-1 nor logic-0, so the signal becomes unknown (or ‘X’) in the absence of Low to High LS.

High to Low Level Shifters

High to Low LS are used for signals crossing from higher voltage domain to lower voltage domain.
It basically attenuates the source signal. 

Although putting a LS for signals crossing from higher voltage domain to lower voltage domain is optional as signals will be interpreted properly in destination domain, but typically we put a LS to avoid stress on the transistors of lower voltage domain due to high voltage of the source signal.

Bi-directional Level Shifters

When dynamic voltage scaling or dynamic voltage freq scaling is used the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high voltage signals and high to low voltage signals.

CLP Report Level Shifter Checks

A few cases when the simulator flags an error are listed below:

• A level shifter cell is required for a crossing, but it is neither present in the design nor specified in the UPF file.
• A level shifter cell is not required for a crossing, but it is either present in the design or specified in the UPF file.
• A level shifter cell is present in the design, but the corresponding strategy is not defined in the UPF file.
• A level shifter strategy is specified in the UPF file, but a level shifter cell is not present in the design.
• The direction of the level shifter cell specified in the UPF file is not correct. For example, instead of a high-to-low level shifter cell, a low-to-high level shifter cell is specified.
• The location of the level shifter cell does not match with the location specified in the UPF file.

CLP Report ISOLATION CHECKS

• An isolation cell is required for a crossing, but it is neither present in the design nor specified in the UPF file.
• An isolation cell is not required for a crossing, but it is either present in the design or specified in the UPF file.
• An isolation cell is present in the design, but the corresponding strategy is not defined in the UPF file.
• An isolation strategy is specified in the UPF file, but an isolation cell is not present in the design.
• Two different clamp values are specified for an isolation cell in the UPF file.
• The isolation clamp value is different from the reset value of the flop.
• The clamp value of the isolation cell in the design does not match the corresponding strategy specified in the UPF file.
• The location of the isolation cell in the design does not match the location specified in the UPF file.
• The isolation control signal is not generated from an always-on region, or is unconnected, floating, or driven by constants.
• The isolation enable signal specified in the UPF file reaches the data pin of the isolation cell or does not reach the enable pin of the isolation cell.
• For an internally isolated IP pin, an isolation cell is present in the design or is specified in the UPF file.
• The isolation control signal is disabled when the source domain is powered-down and the sink domain is powered-up or when the source domain is in a CORRUPT state and the sink domain is not in a CORRPUT state.
• The isolation control signal is active when there is no requirement for isolation.
• The value at the output of an isolation cell is different from that at its input during normal working conditions.
• The value of the isolated port changes during the active isolation period.

isolation cell

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain. 

They clamp the output node to a known voltage.

In the isolation list we specify the clamping value of the nets as logic 0 or logic 1 and accordingly the synthesis tool will insert isolation cells.

Reading in the design: Logic synthesis

The first task in synthesis is to read the design into Design Compiler memory. Reading in an HDL design description consist of two tasks: 

• Analyzing and elaborating the description. 
• The analysis command (analyze) performs the following tasks:  

1. Reads the HDL source and checks it for syntactical errors 
2. Creates HDL library objects in an HDL-independent intermediate format and saves these intermediate files in a specified location

Debug: If the analysis reports errors, they must be fixed, and the design reanalyzed before continuing. 

The elaboration command (elaborate) does  the following:

1. GTECH netlist: Translates the design into a technology-independent design from the intermediate files produced during analysis 
2. Allows changing of parameter values (generics) defined in the source code 
3. Replaces the HDL arithmetic operators in the code with DesignWare components 
4. Automatically executes the link command, which resolves design references 

Debug: you need to  check the elaboration reports carefully to check the number and the type of memory elements Design Compiler thinks it should infer and whether you agree with it or not. Badly modeled hardware description may result as excessive or wrong type of memory elements inferred.  Now, if the elaboration completed successfully, the design is represented in GTECH format: 

 which is an internal, equation-based, technology-independent design format. 

Physics of Power

Dynamic power -> 

Switching Power: is the Power spent ->

Charging and discharging the capacitance of the output net: called load power or CV2 power. Switching power is a function of switching activity and load capacitance, it is data dependent

Short Circuit Power:  is the Power dissipated -> 

Inside the gate when switching, also known as internal power or crowbar power

Total of internal power and switching power called dynamic power

Static Power: is the power when: 

No signals are changing values; means when device is not functional; means the Leakage Power or is a calculation of leakage power called static power

IR Drop: 

Dynamic IR Drop: Dependent on the switching activity of the standard cells themselves.  

                                             Vdynamic_drop = L (di/dt)

1. (RC)max corner -> RCWorst corner. PVT Conditions -> impact of the standard cells. Highest switching activity for standard cells --> ff corner High V & High T  High T > More resistance -> more RC

Static IR drop:  Vstatic_drop = Iavg x Rwire 

Depends on the RC of the power grid connecting the power supply to the respective standard cells

R-> Higher metal layers ->  wide wires -> lower resistance -> low IR drop -> lesser  impact on setup-timing. 

C-> Capacitance of metal wires ->  combination of ground and the coupling capacitance -> if  capacitance is too large -> More IR drop:: 

            Long wire length               - >  Higher wire cap.

            High fan-out of the net       ->  Higher load-cap

            High routing congestion      -> Higher coupling capacitance 

Rectilinear to rectangle script ICC

proc rectlinear2rectangles {rectilinear_boundary} {
set rects [split_polygons -objects [create_poly_rect -boundary $rectilinear_boundary] -output poly_rect]
set count 1

foreach bbox [get_attribute $rects bbox] {
set section$count $bbox
puts "section$count = $bbox"
incr count
  }
}

Now implement like:
rectlinear2rectangles  [get_attr [get_sel] boundary] ]
Reference : icc2

DPT and Color conflict in Physical design

Multiple patterning lithography (MPL) techniques have been used to extend the 193nm lithography to 22nm/14nm nodes.
Possibly further due to the delay of extreme ultra violet lithography and electric beam lithography (EBL) Generally speaking, the MPL consists of double patterning lithography (DPL) and triple patterning lithography (TPL).
There are two main types of DPL with different manufacturing processes:
                  litho-etch-litho-etch (LELE) and
                 self-align double patterning (SADP).
Both of them can be extended for triple patterning. The most important issue for multiple patterning technique is how to successfully decompose the layout into several masks that can be manufactured under current 193nm optical lithography.
 When the pitch between two patterns is less than the lithography threshold, the patterns have to be separated into different masks. This process is called layout decomposition, or coloring. There are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring conflicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay effects
 

Meanwhile, there are studies showing that it is very important to consider the multiple patterning implications at earlier physical design stages so that the overall design and manufacturing closure can be reached.
 Both multiple patterning aware standard cell library design and multiple patterning aware physical design flow are necessary to avoid undecomposable patterns in final layout.

For example, if placement/routing techniques are not multiple patterning friendly, the final layout may introduce some conflicts.
Since redesigning indecomposable patterns in the final layout requires high ECO efforts.



we propose a unified physical design flow for standard cell compliance, pin access, routing, and placement to bridge the gap from mask/layout decomposition to physical design. With further scaling of feature size into very deep sub-wavelength, the mask-level manipulation will be limited if the final layout after physical design is not lithography friendly. Therefore, it is necessary to integrate lithography awareness into nanometer physical design flow. Our preliminary results from such a unified flow are very promising. As multiple patterning lithography is being actively adopted by industry and it can also be used together with EUV, e-beam lithography, DSA, etc., we expect to see more research activies to bridge such gap. 






The double-patterning technology (DPT) that means we can continue to use 193nm lithography to produce features at a 64nm pitch in 20nm processes is a breakthrough for manufacturing but an added complication for design. In double patterning, features that are too close together to be resolved with conventional lithography are separated onto two masks, which are exposed sequentially, with an etch step in between, to form the necessary densely packed features.

Designers must create layouts that can be split (‘decomposed’) into two layers, a process known as coloring, after map-coloring theory. Achieving such layouts means following new design rules that encapsulate the limitations of the lithographic process and prohibit two polygons of the same color from having particular geometric relationships

Physical designers have to work with these new rules during placement and routing, considering the costs of decomposability alongside other costs such as timing, power and area. The physical verification process also has to change, so that it can show that an entire layout can be successfully split onto two masks in a way that meets the foundry’s specifications.
Achieving decomposability

Although foundries will often decompose a layout themselves so that they can optimise the resultant masks for manufacturability, producing decomposable designs means being able to show that applying the foundry rules to a layout can result in successful mask assignments.

The essence of the coloring problem is to create layouts made up of closed loops of polygons (so-called ‘cycles’) that can be given alternating colors along the whole length of the loop. Physical verification tools such as Synopsys’s IC Validator include analysis engines that enable users to define complex geometric relationships, such as the minimum spacing between polygon edges and the corners of facing sides or line ends assigned to the same mask, and then apply them to a candidate design. More elaborate rules allow single polygons to be subdivided on to two masks (a process known as ‘stitching’), which enables greater design freedom by offering a way to avoid some coloring violations.

Meeting DPT requirements in library development

Double-patterning requirements have to be taken into account in both the design and placement of 20nm cell libraries.

Cell designers must ensure that their cell layouts can be safely decomposed into two colors, using physical verification tools to check that their work will meet this requirement and to suggest possible adjustments if it doesn’t. Cell designers also need to think about possible interactions between the cells they design when they are placed adjacent to each other. One way to overcome this issue is to build enough space into every cell that they can’t create coloring violations. The other is to design cells without this margin and rely on the placer to avoid any potential violations caused by cell adjacencies. Both approaches are supported by In-Design technology, which seamlessly couples signoff-quality analysis in IC Validator to the placement engine in IC Compiler.

Here’s an example of a 20nm cell library in which the designer has created an XOR gate and wants to know whether it can be successfully decomposed and its properties in placement.

The cell is first decomposed according to some basic conditions: both power rails must be assigned to the same color and polygons must not be stitched. This approach results in DPT conflicts

Aspect Ratio of Core/Block/Design

The Aspect Ratio of Core/Block/Design is given as:

The aspect ratios of different core shapes are given in below :

The Role of Aspect Ratio on the Design:

1. The aspect ratio effects the routing resources available in the design
2. The aspect ratio effects the congestion
3. The floorplanning need to be done depend on the aspect ratio
4. The placement of the standard cells also effect due to aspect ratio
5. The timing and there by the frequency of the chip also effects due to aspect ratio
6. The clock tree build on the chip also effect due to aspect ratio
7. The placement of the IO pads on the IO area also effects due to aspect ratio
8. The packaging also effects due to the aspect ratio
9. The placement of the chip on the board also effects
10. Ultimately every thing depends on the aspect ration of core/block/design
    

Standard Cell Rows

The area allotted for standard cells on the core is known as standard cell area. This area is divided into the rows known as standard cell rows as shown in the below figure

The height of this row is equal to the height of the standard cell. In digital designs most of the cases, the height of standard cells are constant and width varies. There may be double height cells , triple height cell, etc. Similarly the rows also have heights accordingly. The standard cells will sit in the row with proper orientation.
The rows may abut or may not. The abutted rows share the power connections

Min Pulse Width Violation

Min pulse width check is to ensure that pulse width of clock signal is more than required value.


Basically it is based on frequency of operation and Technology. Means if frequency of design is 1Ghz than typical value of each high and low pulse width will be equal to (1ns/2) 0.5ns if duty cycle is 50%.


Normally we see that in most of design duty cycle always keep 50% otherwise designer can face issues like clock distortion and if in our design using half cycle path means data launch at +ve edge and capturing at -ve edge and again min pulse width as rise level and fall level will not be same and if lots of buffer and inverter will be in chain than it is possible that pulse can be completely vanish.


Also we have to consider the best and worst case when clock get routed and depend on that decide that what should be the required value of Min Pulse Width.


Now we know that rise delay and fall delay of combinational cells are not equal so if a clock entering in a buffer than the output of clock pulse width will be separate to input.
So for example, if buffer rise delay is more than fall delay than output of clock pulse width for high level will be less than input.





so,
High pulse : 0.5-0.056+ 0.049 = 0.493 &
Low pulse : 0.5-0.049+0.056 = 0.507


For better understanding we go with real time scenario for Min Pulse Width.


Normally for clock path we use clock buffer because of the equal rise delay and fall delay of these buffer compare to normal buffer but this delay is not exact equal thatswhy we have to check min pulse width.


We can understand it with an example :-


Lets there is a clock signal which is going to clock pin of flop through series of buffers with different rise and fall delay. we can calculate that how it effect to high or low pulse of clock.

we can understand through calculation:-


High pulse width = 0.5 + (0.049 - 0.056) + (0.034 – 0.039) + (0.023 – 0.026) + (0.042 – 0.046) + (0.061 – 0.061) + (0.051 – 0.054) = 0.478ns

Low Pulse width = 0.5 + (0.056 – 0.049) + (0.038 – 0.034) + (0.026 – 0.023) + (0.046 – 0.042) + (0.061 – 0.061) + (0.054 – 0.051) = 0.522ns



Lets required value of Min pulse width is 0.420ns.

Uncertainty = 80ps
than high pulse width = 0.478-0.080 = 0.398ns
Now we can see that we are getting violation for high pulse as total high pulse width is less than Require value.

Solution

So for solving this violation we can add an inverter which will change the transition and improve it.
as for the the first inverter high pulse will be more then low &  in the next  vice versa.

Crosstalk Questions

What is cross talk?

Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation.



detail click here

How can you avoid crosstalk?

-Double spacing=>more spacing=>less capacitance=>less cross talk

-Multiple vias=>less resistance=>less RC delay

-Shielding=> constant cross coupling capacitance =>known value of crosstalk

-Buffer insertion=>boost the victim strength

How shielding avoids crosstalk problem? What exactly happens there?

-High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD or VSS.

Coupling capacitance remains constant with VDD or VSS.

How spacing helps in reducing crosstalk noise?

width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk

Why double spacing and multiple vias are used related to clock?

Why clock?-- because it is the one signal which chages it state regularly and more compared to any other signal. If any other signal switches fast then also we can use double space.

Double spacing=>width is more=>capacitance is less=>less cross talk

Multiple vias=>resistance in parellel=>less resistance=>less RC delay

How buffer can be used in victim to avoid crosstalk?

Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled signal from aggressor

what is the difference between crosstalk noise and crosstalk delay?
Click here

IR Drop

1. Power

The power spent in Complementary metal oxide semiconductor (CMOS) can be classified as dynamic power consumption and leakage or static power consumption.

2. Leakage power:

is consumed at all times even in ideal states and it is dominating total power equation in advanced technologies. It is unnecessary and need to minimize it.

3. Dynamic power consumption:

is due to the low impedance path between the rails formed through the switching devices. The switching at the output of logic gates can be due to desired functional transitions or due to spurious transitions called glitches. The glitches at the output of logic gates are due to differences in arrival times at various inputs. Glitch power in modern circuits account for 20% to 70% and it is 7% to 43%[1] of the dynamic power consumption.

3.1.Glitch and Dynamic Power

Glitches are the spurious transitions which occur due to difference in arrival times of signals at the gate inputs. These are not needed for the correct functioning of the logic circuit. Power consumed by glitches is called as Glitch power. Every signal net of a gate needs to be transmitted at most once in every clock cycle. But in the real scenario there are output transitions switching more than once in every clock cycle and these unnecessary transitions will also consume power and they contribute significantly to unexpected peak currents which are higher than that of original designs specifications. These peak currents occur in a very short period of time and bring about a large transient voltage or IR drop simultaneously.

The IR drop is a power integrity issue and can impact circuit performance and reliability. So it is very advantageous to eliminate glitches in the circuits as power consumption is critical in today’s chips. The flow of glitch in a digital logic circuit gate is shown in Fig . In a logic gate, the number of edges in the transients at the output of the gate may equal to the number of arriving signals at the gate. The maximum difference in the arrival time of the signals at the inputs of the gate is called as differential path delay. It is also the maximum width of the possible glitch at the circuit output. Consider Fig. 1, in the circuit we can see the unbalanced arrival times of the inputs due to the inverter circuit in the lower input path of the NAND gate

4. How will you do power planning?

Unless Power planning is planned out of the design, power integrity issues like excessive rail voltage drop (IR drop) and ground bounce can create timing problems. In addition, electromigration can lead to chip failures. By using best practices to develop a system-on-a-chip's (SoC's) power structure and analyzing it often throughout the design flow, one can ensure power integrity while preventing a variety of layout difficulties.

Power pads supply power to the chip. Power rings carry power around the periphery of the die, a standard cell's core area, and individual hard macros. Typically, the rings are put in higherlevel routing layers to leave lower layers for signal routing.

1. · There are two types of power planning and management. They are core cell power management and I/O cell power management.
2. · In former one VDD and VSS power rings are formed around the core and macro.
3. · In addition to this straps and trunks are created for macros as per the power requirement.
4. · In the later one, power rings are formed for I/O cells and trunks are constructed between core power ring and power pads.
5. · Top to bottom approach is used for the power analysis of flatten design while bottom up approach is suitable for macros.
6. · The power information can be obtained from the front end design.
7. · The synthesis tool reports static power information.
8. · Dynamic power can be calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL description and test bench.
9. · Exhaustive test coverage is required for efficient calculation of peak power. This methodology is depicted in Figure (1).

5. How can you reduce dynamic power?

-Reduce switching activity by designing good RTL

-Clock gating

-Architectural improvements

-Reduce supply voltage

-Use multiple voltage domains-Multi vdd



Most commonly used methodology to resolve peak transient IR drop is to add the decoupling capacitance (Decap) cells in to layout. These Decap cells acts as local charge reservoirs and reduce the effect of peak IR drop on neighbouring circuits. However Decap cells contribute significant gate tunnelling leakage current to the design and starting from 90nm technologies and below this contribution is even more due to gate oxide scaling.

6. What are the vectors of dynamic power?

I & V

Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. Dynamic IR drop Evaluates the IR drop caused when large amounts of circuitry switch simultaneously.

One of the key requisites is to generate a realistic VCD (Value Change Dump) a file format that captures the switching information which accounts for the real cell and interconnect delays typically done by annotating an SDF (Standard Delay Format) in the gate level simulation.

Such a simulation captures the realistic spread of switching activity in the design for duration of time window (T). During dynamic IR drop analysis T will be break down in to several small time steps.

The length of time step will be determined by the switching activity window or average transition time which can be obtained by the static timing analysis.

Do you know about input vector controlled method of leakage reduction?

Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.

7. If you have both IR drop and congestion how will you fix it?

-Spread macros

-Spread standard cells

-Increase strap width

-Increase number of straps

-Use proper blockage