isolation cell

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain. 

They clamp the output node to a known voltage.

In the isolation list we specify the clamping value of the nets as logic 0 or logic 1 and accordingly the synthesis tool will insert isolation cells.

Physical Design interview 4

What are the inputs you get for Block level Physical Design?

1. Netlist (.v /.vhd)
2. Timing Libraries (.lib/.db)
3. Library Exchange Format (LEF)
4. Technology files (.tf/.tech.lef)
5. Constrains (SDC)
6. Power Specification File
7. Clock Tree Constrains
8. Optimization requirements
9. IO Ports file
10. Floorplan file

What are the different checks you do on the Input Netlist.

1. Floating Pins
2. Unconstrained pins
3. Undriven input ports
4. Unloaded output ports
5. Pin direction mismatches
6. Multiple Drivers
7. Zero wire load Timing checks
8. Issues with respect to the Library file, Timing Constraints, IOs and Optimization requirements.

How to do macro Placement in a block

1. Analyse the fly-line for connectivity between Macros to Macros and between the Macros to IO ports.
2. Group and Place the same hierarchy Macros together.
3. Calculate/Estimate the Channel length required between Macros.
4. Avoid odd shapes
5. Place macros around the block periphery, so that core area will have common logic.
6. Keep enough room around Macros for IO routing.
7. Give necessary blockages around the Macros like Halo around the macros.

What are the issues you see if floorplan is bad.

1. Congestion near Macro corners due to insufficient placement blockage.
2. Standard cell placement in narrow channels led to congestion.
3. Macros of same partition which are placed far apart can cause timing violation.

What are different optimization techniques?

1. Cell Sizing: Size up or down to meet timing/area.
2. Vt Swapping
3. Cloning: fanout reduction
4. Buffering: Buffers are added in the middle of long net paths to reduce the delay.
5. Logical restructuring: Breaking complex cells to simpler cells or vice versa
6. Pin swapping

What are the inputs for the CTS.

1. CTS SDC
2. Max Skew
3. Max and Min Insertion Delay
4. Max Transition, Capacitance, Fanout
5. No of Buffer levels
6. Buffer/Inverter list
7. Clock Tree Routing Metal Layers
8. Clock tree Root pin, Leaf Pin, Preserve pin, through pin and exclude pin

What is Metal Fill

1. Metal Density Rule helps to avoid Over Etching or Metal Erosion.
2. Fill the empty metal tracks with metal shapes to meet the metal density rules.
3. There are two types of Metal Fill
4. Floating Metal Fill: Does not completely shield the aggressor nets, so SI will be there.
5. Grounded Metal Fill: Completely shield the aggressor nets, less SI

Why the Metal Fill is required

1. If there is lot of gap between the routed metal layers (empty tracks), during the process of Etching the etching material used will fall more in this gap due to which Over Etching of existing metal occurs which may create opens. So in order to have uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.

What are the reasons for routing congestion

1. Inefficient floorplan
2. Macro placement or macro channels is not proper.
3. Placement blockages not given
4. No Macro to Macro channel space given.
5. High cell density
6. High local utilization
7. High number of complex cells like AOI/OAI cells which has more pin count are placed together.
8. Placement of std cells near macros
9. Logic optimization is not properly done.
10. Pin density is more on edge of block
11. Buffers added too many while optimization
12. IO ports are crisscrossed, it needs to be properly aligned in order.

What are the different methods to reduce congestion.

1. Review the floorplan/macro placements according to the block size and port placement.
2. Add proper placement blockages in channels and around the macro boundaries.
3. Reduce the local density using the percentage utilization/density screens.
4. Cell padding is applied for high pin density cells, like AOI/OAI.
5. Check and reorder scan chain if needed.
6. Run the congestion driven placement with high effort.
7. Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

Physical design sanity checks

Sanity Checks in Physical Design Flow

1. check_library
2. check_timing
3. report_constraint
4. report_timing
5. report_qor
6. check_design
7. check_legality

check_library:

 check_library validates the libraries i.e., it performs consistency checks between logical and physical libraries, across logical libraries, and within physical libraries. This command checks library qualities in three main areas: Physical library quality Logic versus physical library consistency Logic versus logic library consistency

check_timing 

PNR tool wont optimize the paths which are not constrained. So we have to check any unconstrained paths are exist in the design. check_timing command reports unconstrained paths. If there are any unconstrained paths in the design, run the report_timing_requirements command to verify that the unconstrained paths are false paths.

No clock_relative delay specified for input ports ____________

Unconstrained_endpoints. _________________

End-points are not constrained for maximum delay ___________________

report_constraints

 It reports to check the following parameters. Worst Negative Slack (WNS) Total Negative Slack (TNS) Design Rule Constraint Violations

 report_timing

report_timing displays timing information about a design. The report_timing command provides a report of timing information for the current design. By default, the report_timing command reports the single worst setup path in each clock group. 

report_qor

 report_qor displays QoR information and statistics for the current design. This command reports timing-path group and cell count details, along with current design statistics such as combinational, noncombinational, and total area. The command also reports static power, design rule violations, and compile-time details.

check_design

 check_design checks the current design for consistency. The check_design command checks the internal representation of the current design for consistency, and issues error and warning messages as appropriate. 

a. inputs/Outputs 300

b. Undriven outputs (LINT-5) 505

c. Unloaded inputs (LINT-8) 162

d. Feedthrough (LINT-29) 174

e. Shorted outputs (LINT-31) 52

f. Constant outputs (LINT-52) 24

g. Cells 152

h. Cells do not drive (LINT-1) 1

i. Connected to power or ground (LINT-32) 118

j. Nets connected to multiple pins on same cell (LINT-33) 33

k. Nets 1226

l. Unloaded nets (LINT-2) 721

Error messages indicate design problems of such severity that the compile command does not accept the design Warning messages are informational and do not necessarily indicate design problems. However, these messages should be investigated.

Warnings

Potential problems detected by this command include Unloaded input ports or undriven output ports Nets without loads or drivers or with multiple drivers

Cells or designs without inputs or outputs 

Mismatched pin counts between an instance and its reference 

Tristate buses with non-tristate drivers wire loops across hierarchies

 check_legality 

reports overlap and cells placement related violation like orientation, overlaps etc.