Reading in the design: Logic synthesis

The first task in synthesis is to read the design into Design Compiler memory. Reading in an HDL design description consist of two tasks: 

• Analyzing and elaborating the description. 
• The analysis command (analyze) performs the following tasks:  

1. Reads the HDL source and checks it for syntactical errors 
2. Creates HDL library objects in an HDL-independent intermediate format and saves these intermediate files in a specified location

Debug: If the analysis reports errors, they must be fixed, and the design reanalyzed before continuing. 

The elaboration command (elaborate) does  the following:

1. GTECH netlist: Translates the design into a technology-independent design from the intermediate files produced during analysis 
2. Allows changing of parameter values (generics) defined in the source code 
3. Replaces the HDL arithmetic operators in the code with DesignWare components 
4. Automatically executes the link command, which resolves design references 

Debug: you need to  check the elaboration reports carefully to check the number and the type of memory elements Design Compiler thinks it should infer and whether you agree with it or not. Badly modeled hardware description may result as excessive or wrong type of memory elements inferred.  Now, if the elaboration completed successfully, the design is represented in GTECH format: 

 which is an internal, equation-based, technology-independent design format.