Crosstalk Questions

What is cross talk?

Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation.



detail click here

How can you avoid crosstalk?

-Double spacing=>more spacing=>less capacitance=>less cross talk

-Multiple vias=>less resistance=>less RC delay

-Shielding=> constant cross coupling capacitance =>known value of crosstalk

-Buffer insertion=>boost the victim strength

How shielding avoids crosstalk problem? What exactly happens there?

-High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD or VSS.

Coupling capacitance remains constant with VDD or VSS.

How spacing helps in reducing crosstalk noise?

width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk

Why double spacing and multiple vias are used related to clock?

Why clock?-- because it is the one signal which chages it state regularly and more compared to any other signal. If any other signal switches fast then also we can use double space.

Double spacing=>width is more=>capacitance is less=>less cross talk

Multiple vias=>resistance in parellel=>less resistance=>less RC delay

How buffer can be used in victim to avoid crosstalk?

Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled signal from aggressor

what is the difference between crosstalk noise and crosstalk delay?
Click here

IR Drop

1. Power

The power spent in Complementary metal oxide semiconductor (CMOS) can be classified as dynamic power consumption and leakage or static power consumption.

2. Leakage power:

is consumed at all times even in ideal states and it is dominating total power equation in advanced technologies. It is unnecessary and need to minimize it.

3. Dynamic power consumption:

is due to the low impedance path between the rails formed through the switching devices. The switching at the output of logic gates can be due to desired functional transitions or due to spurious transitions called glitches. The glitches at the output of logic gates are due to differences in arrival times at various inputs. Glitch power in modern circuits account for 20% to 70% and it is 7% to 43%[1] of the dynamic power consumption.

3.1.Glitch and Dynamic Power

Glitches are the spurious transitions which occur due to difference in arrival times of signals at the gate inputs. These are not needed for the correct functioning of the logic circuit. Power consumed by glitches is called as Glitch power. Every signal net of a gate needs to be transmitted at most once in every clock cycle. But in the real scenario there are output transitions switching more than once in every clock cycle and these unnecessary transitions will also consume power and they contribute significantly to unexpected peak currents which are higher than that of original designs specifications. These peak currents occur in a very short period of time and bring about a large transient voltage or IR drop simultaneously.

The IR drop is a power integrity issue and can impact circuit performance and reliability. So it is very advantageous to eliminate glitches in the circuits as power consumption is critical in today’s chips. The flow of glitch in a digital logic circuit gate is shown in Fig . In a logic gate, the number of edges in the transients at the output of the gate may equal to the number of arriving signals at the gate. The maximum difference in the arrival time of the signals at the inputs of the gate is called as differential path delay. It is also the maximum width of the possible glitch at the circuit output. Consider Fig. 1, in the circuit we can see the unbalanced arrival times of the inputs due to the inverter circuit in the lower input path of the NAND gate

4. How will you do power planning?

Unless Power planning is planned out of the design, power integrity issues like excessive rail voltage drop (IR drop) and ground bounce can create timing problems. In addition, electromigration can lead to chip failures. By using best practices to develop a system-on-a-chip's (SoC's) power structure and analyzing it often throughout the design flow, one can ensure power integrity while preventing a variety of layout difficulties.

Power pads supply power to the chip. Power rings carry power around the periphery of the die, a standard cell's core area, and individual hard macros. Typically, the rings are put in higherlevel routing layers to leave lower layers for signal routing.

1. · There are two types of power planning and management. They are core cell power management and I/O cell power management.
2. · In former one VDD and VSS power rings are formed around the core and macro.
3. · In addition to this straps and trunks are created for macros as per the power requirement.
4. · In the later one, power rings are formed for I/O cells and trunks are constructed between core power ring and power pads.
5. · Top to bottom approach is used for the power analysis of flatten design while bottom up approach is suitable for macros.
6. · The power information can be obtained from the front end design.
7. · The synthesis tool reports static power information.
8. · Dynamic power can be calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL description and test bench.
9. · Exhaustive test coverage is required for efficient calculation of peak power. This methodology is depicted in Figure (1).

5. How can you reduce dynamic power?

-Reduce switching activity by designing good RTL

-Clock gating

-Architectural improvements

-Reduce supply voltage

-Use multiple voltage domains-Multi vdd



Most commonly used methodology to resolve peak transient IR drop is to add the decoupling capacitance (Decap) cells in to layout. These Decap cells acts as local charge reservoirs and reduce the effect of peak IR drop on neighbouring circuits. However Decap cells contribute significant gate tunnelling leakage current to the design and starting from 90nm technologies and below this contribution is even more due to gate oxide scaling.

6. What are the vectors of dynamic power?

I & V

Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. Dynamic IR drop Evaluates the IR drop caused when large amounts of circuitry switch simultaneously.

One of the key requisites is to generate a realistic VCD (Value Change Dump) a file format that captures the switching information which accounts for the real cell and interconnect delays typically done by annotating an SDF (Standard Delay Format) in the gate level simulation.

Such a simulation captures the realistic spread of switching activity in the design for duration of time window (T). During dynamic IR drop analysis T will be break down in to several small time steps.

The length of time step will be determined by the switching activity window or average transition time which can be obtained by the static timing analysis.

Do you know about input vector controlled method of leakage reduction?

Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.

7. If you have both IR drop and congestion how will you fix it?

-Spread macros

-Spread standard cells

-Increase strap width

-Increase number of straps

-Use proper blockage

Congestion

Congestion needs to be analyzed after placement and the routing results depend on how congested your design is. Routing congestion may be localized. Some of the things that you can do to make sure routing is hassle free are:

Placement blockages: 

The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages.
Soft blockages (buffer only)
Hard blockages (No std cells and buffers are allowed to Place)
Partial blockages (same as density screens)
Halo (same as soft blockage but blockage can also be moved w.r.t Macro.)

Macro-padding:

 Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pin outs of the macros, thereby giving extra breathing space for the macro pin connections to standard cells.

Cell padding:

Cell Padding refers to placement clearance applied to std cells in PnR tools. This is typically done to ease placement congestion or reserve some space for future use down the flow.
For example typically people apply cell padding to the buffers/inverters used to build clock tree, so that space is reserved to insert DECAP cells near them after CTS.

Cell padding adds hard constraints to placement. The constraints are honored by cell legalization, CTS, and timing optimization, unless the padding is reset after placement so
those operations can use the reserved space. You can use cell padding to reserve space for routing.

The command "specifyCellPad" is used to specify the cell padding in SOC-Encounter.

This command adds padding on the right side of library cells during placement.

The padding is specified in terms of a factor that is applied to the metal2 pitch. For example, if you specify a factor of 2, the software ensures that there is additional clearance of two times the metal2 pitch on the right side of the specified cells.

Maximum Utilization constraint (density screens): 

Some tools let you specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing.
each tool is having this setting, check wityh your DA for the detail.

set_congestion_options -max_util .6 -coordinate {10 20 40 40}

Physical Design interview 4

What are the inputs you get for Block level Physical Design?

1. Netlist (.v /.vhd)
2. Timing Libraries (.lib/.db)
3. Library Exchange Format (LEF)
4. Technology files (.tf/.tech.lef)
5. Constrains (SDC)
6. Power Specification File
7. Clock Tree Constrains
8. Optimization requirements
9. IO Ports file
10. Floorplan file

What are the different checks you do on the Input Netlist.

1. Floating Pins
2. Unconstrained pins
3. Undriven input ports
4. Unloaded output ports
5. Pin direction mismatches
6. Multiple Drivers
7. Zero wire load Timing checks
8. Issues with respect to the Library file, Timing Constraints, IOs and Optimization requirements.

How to do macro Placement in a block

1. Analyse the fly-line for connectivity between Macros to Macros and between the Macros to IO ports.
2. Group and Place the same hierarchy Macros together.
3. Calculate/Estimate the Channel length required between Macros.
4. Avoid odd shapes
5. Place macros around the block periphery, so that core area will have common logic.
6. Keep enough room around Macros for IO routing.
7. Give necessary blockages around the Macros like Halo around the macros.

What are the issues you see if floorplan is bad.

1. Congestion near Macro corners due to insufficient placement blockage.
2. Standard cell placement in narrow channels led to congestion.
3. Macros of same partition which are placed far apart can cause timing violation.

What are different optimization techniques?

1. Cell Sizing: Size up or down to meet timing/area.
2. Vt Swapping
3. Cloning: fanout reduction
4. Buffering: Buffers are added in the middle of long net paths to reduce the delay.
5. Logical restructuring: Breaking complex cells to simpler cells or vice versa
6. Pin swapping

What are the inputs for the CTS.

1. CTS SDC
2. Max Skew
3. Max and Min Insertion Delay
4. Max Transition, Capacitance, Fanout
5. No of Buffer levels
6. Buffer/Inverter list
7. Clock Tree Routing Metal Layers
8. Clock tree Root pin, Leaf Pin, Preserve pin, through pin and exclude pin

What is Metal Fill

1. Metal Density Rule helps to avoid Over Etching or Metal Erosion.
2. Fill the empty metal tracks with metal shapes to meet the metal density rules.
3. There are two types of Metal Fill
4. Floating Metal Fill: Does not completely shield the aggressor nets, so SI will be there.
5. Grounded Metal Fill: Completely shield the aggressor nets, less SI

Why the Metal Fill is required

1. If there is lot of gap between the routed metal layers (empty tracks), during the process of Etching the etching material used will fall more in this gap due to which Over Etching of existing metal occurs which may create opens. So in order to have uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.

What are the reasons for routing congestion

1. Inefficient floorplan
2. Macro placement or macro channels is not proper.
3. Placement blockages not given
4. No Macro to Macro channel space given.
5. High cell density
6. High local utilization
7. High number of complex cells like AOI/OAI cells which has more pin count are placed together.
8. Placement of std cells near macros
9. Logic optimization is not properly done.
10. Pin density is more on edge of block
11. Buffers added too many while optimization
12. IO ports are crisscrossed, it needs to be properly aligned in order.

What are the different methods to reduce congestion.

1. Review the floorplan/macro placements according to the block size and port placement.
2. Add proper placement blockages in channels and around the macro boundaries.
3. Reduce the local density using the percentage utilization/density screens.
4. Cell padding is applied for high pin density cells, like AOI/OAI.
5. Check and reorder scan chain if needed.
6. Run the congestion driven placement with high effort.
7. Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

POCV

Advanced on-chip variation (AOCV) analysis reduces unnecessary pessimism by taking the design methodology and fabrication process variation into account. AOCV determines derating factors based on metrics of path logic depth and the physical distance traversed by a particular path. A longer path that has more gates tends to have less total variation because the random variations from gate to gate tend to cancel each other out. A path that spans a larger physical distance across the chip tends to have larger systematic variations. AOCV is less pessimistic than a traditional OCV analysis, which relies on constant derating factors that do not take path-specific metrics into account.

The AOCV analysis determines path-depth and location-based bounding box metrics to calculate a context-specific AOCV derating factor to apply to a path, replacing the use of a constant derating factor.

AOCV analysis works with all other PrimeTime features and affects all reporting commands. This solution works in both the Standard Delay Format (SDF)-based and the delay calculation based flows.

PrimeTime ADV parametric on-chip variation (POCV) models the delay of an instance as a function of a variable that is specific to the instance. That is, the instance delay is parameterized as a function of the unique delay variable for the instance.

POCV uses a statistical approach, but it doesn’t do a full SSTA analysis. Instead, it calculates delay variation by modeling the intrinsic cell delay and load parasitics (line resistance, line capacitance, and load capacitance) to determine both the mean and “sigma” (variation) of a logic stage. The cell delay can be further broken into an n-channel component and a p-channel component. They then assume that all the cells along a path have the same mean and sigma.



This means that a given path doesn’t have to be analyzed stage-by-stage; the number of stages can be counted, with the basic stage delay mean and sigma then used to calculate the path delay and accumulated variation. They claim that this keeps the run times down to just over what standard STA tools require, far faster than SSTA. They also claim speedier execution and greater accuracy than AOCV, and no derating tables are required.


POCV) is a technique that has been proposed as a means of reducing pessimism further by taking elements of SSTA and implementing them in a way that is less compute-intensive.
POCV provides the following:

•Statistical single-parameter derating for random variations

•Single input format and characterization source for both AOCV and POCV table data

•Nonstatistical timing reports

•Limited statistical reporting (mean, sigma) for timing paths

•Compatibility with existing PrimeTime functionality, except PrimeTime VX

Compared to AOCV, POCV provides

•Reduced pessimism gap between graph-based analysis and path-based analysis

•Less overhead for incremental timing analysis

Physical design sanity checks

Sanity Checks in Physical Design Flow

1. check_library
2. check_timing
3. report_constraint
4. report_timing
5. report_qor
6. check_design
7. check_legality

check_library:

 check_library validates the libraries i.e., it performs consistency checks between logical and physical libraries, across logical libraries, and within physical libraries. This command checks library qualities in three main areas: Physical library quality Logic versus physical library consistency Logic versus logic library consistency

check_timing 

PNR tool wont optimize the paths which are not constrained. So we have to check any unconstrained paths are exist in the design. check_timing command reports unconstrained paths. If there are any unconstrained paths in the design, run the report_timing_requirements command to verify that the unconstrained paths are false paths.

No clock_relative delay specified for input ports ____________

Unconstrained_endpoints. _________________

End-points are not constrained for maximum delay ___________________

report_constraints

 It reports to check the following parameters. Worst Negative Slack (WNS) Total Negative Slack (TNS) Design Rule Constraint Violations

 report_timing

report_timing displays timing information about a design. The report_timing command provides a report of timing information for the current design. By default, the report_timing command reports the single worst setup path in each clock group. 

report_qor

 report_qor displays QoR information and statistics for the current design. This command reports timing-path group and cell count details, along with current design statistics such as combinational, noncombinational, and total area. The command also reports static power, design rule violations, and compile-time details.

check_design

 check_design checks the current design for consistency. The check_design command checks the internal representation of the current design for consistency, and issues error and warning messages as appropriate. 

a. inputs/Outputs 300

b. Undriven outputs (LINT-5) 505

c. Unloaded inputs (LINT-8) 162

d. Feedthrough (LINT-29) 174

e. Shorted outputs (LINT-31) 52

f. Constant outputs (LINT-52) 24

g. Cells 152

h. Cells do not drive (LINT-1) 1

i. Connected to power or ground (LINT-32) 118

j. Nets connected to multiple pins on same cell (LINT-33) 33

k. Nets 1226

l. Unloaded nets (LINT-2) 721

Error messages indicate design problems of such severity that the compile command does not accept the design Warning messages are informational and do not necessarily indicate design problems. However, these messages should be investigated.

Warnings

Potential problems detected by this command include Unloaded input ports or undriven output ports Nets without loads or drivers or with multiple drivers

Cells or designs without inputs or outputs 

Mismatched pin counts between an instance and its reference 

Tristate buses with non-tristate drivers wire loops across hierarchies

 check_legality 

reports overlap and cells placement related violation like orientation, overlaps etc.

SPEF : Standard Parasitic Exchange Format

SPEF (Standard Parasitic Exchange Format) is documented in chapter 9 of IEEE 1481-1999. Several methods of describing parasitics are documented, but we are discussing only few important one.
General Syntax

A typical SPEF file will have 4 main sections

– a header section,
– a name map section,
– a top level port section and
– the main parasitic description section.

Generally, SPEF keywords are preceded with a *. For example, *R_UNIT, *NAME_MAP and *D_NET.

Comments start anywhere on a line with // and run to the end of the line. Each line in a block of comments must start with //.
Header Information

The header section is 14 lines containing information about

– the design name,
– the parasitic extraction tool,
– naming styles
– and units.

When reading SPEF, it is important to check the header for units as they vary across tools. By default, SPEF from Astro will be in pF and kOhm while SPEF from Star-RCXT will be in fF and Ohm.
Name Map Section

To reduce file size, SPEF allows long names to be mapped to shorter numbers preceded by a *. This mapping is defined in the name map section. For example:

*NAME_MAP

*509 F_C_EP2
*510 F_C_EP3
*511 TOP/BUF_ZCLK_2_pin_Z_1


Later in the file, F_C_EP2 can be referred to by its name or by *509. Name mapping in SPEF is not required. Also, mapped and non-mapped names can appear in the same file. Typically, short names such as a pin named A will not be mapped as mapping would not reduce file size. You can write a script will map the numbers back into names. This will make SPEF easier to read, but greatly increase file size.
Port Section

The port section is simply a list of the top level ports in a design. They are also annotated as input, output or bidirect with an I, O or B. For example:

*PORTS

*1 I
*2 I
*3 O
*4 O
*5 O

Parasitics

Each extracted net will have a *D_NET section. This will usually consist of a *D_NET line, a *CONN section, a *CAP section, *RES section and a *END line. Single pin nets will not have a *RES section. Nets connected by abutting pins will not have a *CAP section.

*D_NET regcontrol_top/GRC/n13345 1.94482

*CONN

*I regcontrol_top/GRC/U9743:E I *C 537.855 9150.11 *L 3.70000

*I regcontrol_top/GRC/U9409:A I *C 540.735 9146.02 *L 5.40000

*I regcontrol_top/GRC/U9407:Z O *C 549.370 9149.88 *D OR2M1P

*CAP

1 regcontrol_top/GRC/U9743:E 0.936057

2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675

3 regcontrol_top/GRC/U9407:Z 0.386093

*RES

1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916

2 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9409:A 8.07710

3 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U9407:Z 11.9156

*END

The *D_NET line tells the net name and the net's total capacitance. This capacitance will be the sum of all the capacitances in the *CAP section.

*CONN Section

The *CONN section lists the pins connected to the net. A connection to a cell instance starts with a *I. A connection to a top level port starts with a *P.

The syntax of the *CONN entries is:

*I *C

Where:
– The pin name is the name of the pin.
– The direction will be I, O or B for input, output or bidirect.
– The xy coordinate will be the location of the pin in the layout.
– For an input, the loading information will be *L and the pin's capacitance.
– For an output, the driving information will be *D and the driving cell's type.
– Coordinates for *P port entries may not be accurate because some extraction tools look for the physical location of the logical port (which does not exist) rather then the location of the corresponding pin.

*CAP Section

 The *CAP section provides detailed capacitance information for the net. Entries in the *CAP section come in two forms, one for a capacitor lumped to ground and one for a coupled capacitor.
A capacitor lumped to ground has three fields,
– an identifying integer,
– a node name and
– the capacitance value of this node

– e.g

o 1 regcontrol_top/GRC/U9743:E 0.936057

A coupling capacitor has four fields,
– an identifying integer,
– two node names and
– The values of the coupling capacitor between these two nodes

– E.g

o 2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675
If netA is coupled to netB, the coupling capacitor will be listed in each net's *CAP section.

*RES Section

 The *RES section provides the resistance network for the net.
Entries in *RES section contain 4 fields,
– an identifying integer,
– two node names and
– the resistance between these two nodes.

– E.g

o 1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916
The resistance network for a net can be very complex. SPEF can contain resistor loops or seemingly ridiculously huge resistors even if the layout is a simple point to point route. This is due how the extraction tool cuts nets into tiny pieces for extraction and then mathematically stitches them back together when writing SPEF.

Parasitic Values The above examples show a single parasitic value for each capacitor or resistor. It is up to the parasitic extraction and delay calculation flow to decide which corner this value represents. SPEF also allows for min:typ:max values to be reported:
1 regcontrol_top/GRC/U9743:E 0.936057:1.02342:1.31343

The IEEE standard requires either 1 or 3 values to be reported. However, some tools will report min:max pairs and it is expected that tools may report many corners (corner1:corner2:corner3:corner4) in the future.

Library Exchange Format (LEF)

Library Exchange Format (LEF) is a specification for representing the physical layout of an integrate circuit in an ASCII format. It includes design rules and abstract information about the cells. LEF is used in conjunction with Design Exchange Format (DEF) to represent the complete physical layout of an integrated circuit while it is being designed.


An ASCII data format, used to describe a standard cell library Includes the design rules for routing and the Abstract of the cells, no information about the internal netlist of the cells
A LEF file contains the following sections:
Technology:
Layer
Design rules,
via definitions,
Metal capacitance

 Site: Site extension
 Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances.

The technology is described by the Layer and Via statements. To each layer the following attributes may be associated:

Type: Layer type can be routing, cut (contact), masterslice (poly, active),overlap.

 width/pitch/spacing rules
 direction
resistance and capacitance per unit square
antenna Factor

Layers are defined in process order from bottom to top

poly masterslice
cc cut
metal1 routing
via cut
metal2 routing
via2 cut
metal3 routing
Cut Layer definition

LAYER
layername
TYPE CUT ;
SPACING Specifies the minimum spacing allowed between via cuts on the same net or different nets. This value can be overridden by the SAMENET SPACING statement (we are going to use this statement later)END layerName

Implant Layer definition

LAYER layerName
TYPE IMPLANT ;
SPACING minSpacing
END layerName

Defines implant layers in the design. Each layer is defined by assigning it a name and simple spacing and width rules. These spacing and width rules only affect the legal cell placements. These rules interact with the library methodology, detailed placement, and filler cell support.

Masterslice or Overlap Layer definition
LAYER layerName
TYPE {MASTERSLICE | OVERLAP} ;

Defines masterslice (nonrouting) or overlap layers in the design. Masterslice layers are typically polysilicon layers and are only needed if the cell MACROs have pins on the polysilicon layer.

Routing Layer definition

LAYER layerName
TYPE ROUTING ;
DIRECTION {HORIZONTAL | VERTICAL} ;
PITCH distance;
WIDTH defWidth;
OFFSET distance ;
SPACING minSpacing;

RESISTANCE RPERSQ value ;

Specifies the resistance for a square of wire, in ohms per square. The resistance of a wire can be defined as RPERSQU x wire length/wire width


CAPACITANCE CPERSQDIST value ;

Specifies the capacitance for each square unit, in picofarads per square micron. This is used to model wire-to-ground capacitance.

Manufacturing Grid

MANUFACTURINGGRID value ;

Defines the manufacturing grid for the design. The manufacturing grid is used for geometry alignment. When specified, shapes and cells are placed in locations that snap to the manufacturing grid.

Via

VIA viaName
DEFAULT
TOPOFSTACKONLY
FOREIGN foreignCellName [pt [orient]] ;
RESISTANCE value ;

{LAYER layerName ;
{RECT pt pt ;} ...} ...
END viaName


Defines vias for usage by signal routers. Default vias have exactly three layers used:

A cut layer, and two layers that touch the cut layer (routing or masterslice). The cut layer rectangle must be between the two routing or masterslice layer rectangles.

Via Rule Generate
VIARULE viaRuleName GENERATE
LAYER routingLayerName ;
{ DIRECTION {HORIZONTAL | VERTICAL} ;
OVERHANG overhang ;
METALOVERHANG metalOverhang ;
| ENCLOSURE overhang1 overhang2 ;}
LAYER routingLayerName ;

{ DIRECTION {HORIZONTAL | VERTICAL} ;


OVERHANG overhang ;
METALOVERHANG metalOverhang ;
| ENCLOSURE overhang1 overhang2 ;}


LAYER cutLayerName ;
RECT pt pt ;
SPACING xSpacing BY ySpacing ;

RESISTANCE resistancePerCut ;
END viaRuleName


Defines formulas for generating via arrays. Use the VIARULE GENERATE statement to cover special wiring that is not explicitly defined in the VIARULE statement.

Same-Net Spacing
SPACING
SAMENET layerName layerName minSpace [STACK] ; ...
END SPACING

Defines the same-net spacing rules. Same-net spacing rules determine minimum spacing between geometries in the same net and are only required if same-net spacing is smaller than different-net spacing, or if vias on different layers have special stacking rules.


Thesespecifications are used for design rule checking by the routing and verification tools.


Spacing is the edge-to-edge separation, both orthogonal and diagonal.
Site

SITE siteName

CLASS {PAD | CORE} ;


[SYMMETRY {X | Y | R90} ... ;] (will discuss this later in macro definition)


SIZE width BY height ;

END siteName

Macro

MACRO macroName

[CLASS { COVER [BUMP] |
 RING |
 BLOCK [BLACKBOX]

| PAD [INPUT | OUTPUT |INOUT | POWER | SPACER | AREAIO]


| CORE [FEEDTHRU | TIEHIGH | TIELOW | SPACER | ANTENNACELL]

| ENDCAP {PRE | POST | TOPLEFT | TOPRIGHT | BOTTOMLEFT | BOTTOMRIGHT}


}

;]


[SOURCE {USER | BLOCK} ;]

[FOREIGN foreignCellName [pt [orient]] ;] ...


[ORIGIN pt ;]

[SIZE width BY height ;]

[SYMMETRY {X | Y | R90} ... ;]


[SITE siteName ;]

[PIN statement] ...


[OBS statement] ...

Macro Pin Statement

PIN pinName

FOREIGN foreignPinName [STRUCTURE [pt [orient] ] ] ;

[DIRECTION {INPUT | OUTPUT [TRISTATE] | INOUT | FEEDTHRU} ;]


[USE { SIGNAL | ANALOG | POWER | GROUND | CLOCK } ;]


[SHAPE {ABUTMENT | RING | FEEDTHRU} ;]


[MUSTJOIN pinName ;]

{PORT


[CLASS {NONE | CORE} ;]

{layerGeometries} ...

END} ...


END pinName]
Macro Obstruction Statement

OBS

{ LAYER layerName [SPACING minSpacing | DESIGNRULEWIDTH value] ;


RECT pt pt ;


POLYGON pt pt pt pt ... ;

END