physical design interview2

Explain the flow of physical design and inputs and outputs for each step in flow.

The physical design flow is generally explained in the Figure

 (1.). In each section of the flow EDA tools available from the two main EDA companies-Synopsys and Cadence is also listed. In each and every step of the flow timing and power analysis can be carried out. If timing and power requirements are not met then either the whole flow has to be re-exercised or going back one or two steps and optimizing the design or incremental optimization may meet the requirements

What is cell delay and net delay?

Gate delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

Gate delay =function of(i/p transition time, Cnet+Cpin).

Cell delay is also same as Gate delay.

Cell delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

Intrinsic delay

Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

Wire delay =fn(Rnet , Cnet+Cpin)

What are delay models and what is the difference between them?

1. Linear Delay Model (LDM)
2. Non Linear Delay Model (NLDM)

What is wire load model?

Wire load model is NLDM which has estimated R and C of the net.

Why higher metal layers are preferred for Vdd and Vss?

1. Because it has less resistance and hence leads to less IR drop.

What is logic optimization and give some methods of logic optimization.

1. Upsizing
2. Downsizing
3. Buffer insertion
4. Buffer relocation
5. Dummy buffer placement

What is the significance of negative slack?

1. negative slack==> there is setup voilation==> deisgn can fail

What is signal integrity? How it affects Timing?

1. IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.
2. If Idrop is more==>delay increases.
3. crosstalk==>there can be setup as well as hold voilation.

What is IR drop? How to avoid? How it affects timing?

1. There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.
2. If IR drop is more==>delay increases.

What is EM and it effects?

1. Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.
3. Affects: Either short or open of the signal line or power line.

What are types of routing?

1. Global Routing
2. Track Assignment
3. Detail Routing

What is latency? Give the types?

Source Latency

1. It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".
3. Delay from clock source to beginning of clock tree (i.e. clock definition point).
5. The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network latency

1. It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".
3. The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is track assignment?

1. Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

What is congestion?

1. If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

Whether congestion is related to placement or routing?

1. Routing

What are clock trees?

1. Distribution of clock from the clock source to the sync pin of the registers.

What are clock tree types?

1. H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is cloning and buffering?

1. Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
2. Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy

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Physical design part1
Physical design part2
Physical design part3
Placement

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