physical design interview1

What parameters (or aspects) differentiate Chip Design and Block level design?

1. Chip design has I/O pads; block design has pins.
2. Chip design uses all metal layes available; block design may not use all metal layers.
3. Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
4. Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design?

1. First check fly lines i.e. check net connections from macro to macro and macro to standard cells.
2. If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.
3. If input pin is connected to macro better to place nearer to that pin or pad.
4. If macro has more connection to standard cells spread the macros inside core.
5. Avoid criscross placement of macros.
6. Use soft or hard blockages to guide placement engine.

Differentiate between a Hierarchical Design and flat design?

1. Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.
2. Hierarchical design takes more run time; Flattened design takes less run time.

Which is more complicated when u have a 48 MHz and 500 MHz clock design?

1. 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

Name few tools which you used for physical verification?

1. Herculis from Synopsys, Caliber from Mentor Graphics.

What are the input files will you give for primetime correlation?

1. Netlist, Technology library, Constraints, SPEF or SDF file.

If the routing congestion exists between two macros, then what will you do?

1. Provide soft or hard blockage

How will you decide the die size?

1. By checking the total area of the design you can decide die size.

If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?

1. Poly

If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

1. Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

In your project what is die size, number of metal layers, technology, foundry, number of clocks?

1. Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!
2. Metal layers: See your tech file. generally for 90nm it is 7 to 9.
3. Technology: Again look into tech files.
4. Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc
5. Clocks: Look into your design and SDC file !

How many macros in your design?

1. You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

What is each macro size and number of standard cell count?

1. Depends on your design.

What are the input needs for your design?

1. For synthesis: RTL, Technology library, Standard cell library, Constraints
2. For Physical design: Netlist, Technology library, Constraints, Standard cell library

What is SDC constraint file contains?

1. Clock definitions
2. Timing exception-multicycle path, false path
3. Input and Output delays

How did you do power planning?

How to calculate core ring width, macro ring width and strap or trunk width?
How to find number of power pad and IO power pads?
How the width of metal and number of straps calculated for power and ground?

1. Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.
2. How to find total chip power?
3. Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

What are the problems faced related to timing?

1. Prelayout: Setup, Max transition, max capacitance
2. Post layout: Hold

How did you resolve the setup and hold problem?

1. Setup: upsize the cells
2. Hold: insert buffers

In which layer do you prefer for clock routing and why?

Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

If in your design has reset pin, then it’ll affect input pin or output pin or both?

Output pin.

During power analysis, if you are facing IR drop problem, then how did you avoid?

1. Increase power metal layer width.
2. Go for higher metal layer.
3. Spread macros or standard cells.
4. Provide more straps.

Define antenna problem and how did you resolve these problem?

1. Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.
2. Decrease the length of the net by providing more vias and layer jumping.
3. Insert antenna diode.

How delays vary with different PVT conditions? Show the graph.

1. P increase--> dealy increase
2. P decrease--> delay decrease
3. V increase--> delay decrease
4. V decrease--> delay increase
5. T increase--> delay increase
6. T decrease--> delay decrease

Learn More ==>
Physical design part1
Physical design part2
Physical design part3
Placement

verilog interview question part1
verilog interview question part2
verilog interview question part3