Verilog interview question part3

How can I override variables in an automatic task?

By default, all variables in a module are static, i.e., these variables will be replicated for all instances of a module. However, in the case of task and function, either the task/function itself or the variables within them can be defined as static or automatic. The following explains the inferences through different combinations of the task/function and/or its variables, declared either as static or automatic:

 

No automatic definition of task/function or its variables This is the Verilog-1995 format, wherein the task/function and its variables were implicitly static. The variables are allocated only once. Without the mention of the automatic keyword, multiple calls to task/function will override their variables.

Static task/function definition

System Verilog introduced the keyword static. When a task/function is explicitly defined as static, then its variables are allocated only once, and can be overridden. This scenario is exactly the same scenario as before.

Automatic task/function definition

From Verilog-2001 onwards, and included within SystemVerilog, when the task/function is declared as automatic, its variables are also implicitly automatic. Hence, during multiple calls of the task/function, the variables are allocated each time and replicated without any overwrites.

Static task/function and automatic variables

SystemVerilog also allows the use of automatic variables in a static task/function. Those without any changes to automatic variables will remain implicitly static. This will be useful in scenarios wherein the implicit static variables need to be initialised before the task call, and the automatic variables can be allocated each time.

Automatic task/function and static variables

SystemVerilog also allows the use of static variables in an automatic task/function. Those without any changes to static variables will remain implicitly automatic. This will be useful in scenarios wherein the static variables need to be updated for each call, whereas the rest can be allocated each time.

What are the rules governing usage of a Verilog function?

The following rules govern the usage of a Verilog function construct:

A function cannot advance simulation-time, using constructs like #, @. etc.
A function shall not have nonblocking assignments.
A function without a range defaults to a one bit reg for the return value.

It is illegal to declare another object with the same name as the function in the scope where the function is declared.

How do I prevent selected parameters of a module from being overridden during instantiation?

If a particular parameter within a module should be prevented from being overridden, then it should be declared using the localparam construct, rather than the parameter construct. The localparam construct has been introduced from Verilog-2001. Note that a localparam variable is fully identical to being defined as a parameter, too. In the following example, the localparam construct is used to specify num_bits, and hence trying to override it directly gives an error message.





Note, however, that, since the width and depth are specified using the parameter construct, they can be overridden during instantiation or using defparam, and hence will indirectly override the num_bits values. In general, localparam constructs are useful in defining new and localized identifiers whose values are derived from regular parameters.

What are the pros and cons of specifying the parameters using the defparam construct vs. specifying during instantiation?

The advantages of specifying parameters during instantiation method are:

All the values to all the parameters don’t need to be specified. Only those parameters that are assigned the new values need to be specified. The unspecified parameters will retain their default values specified within its module definition.

The order of specifying the parameter is not relevant anymore, since the parameters are directly specified and linked by their name.

The disadvantage of specifying parameter during instantiation are:

This has a lower precedence when compared to assigning using defparam.
The advantages of specifying parameter assignments using defparam are:
This method always has precedence over specifying parameters during instantiation.
All the parameter value override assignments can be grouped inside one module and together in one place, typically in the top-level testbench itself.

When multiple defparams for a single parameter are specified, the parameter takes the value of the last defparam statement encountered in the source if, and only if, the multiple defparam’s are in the same file. If there are defparam’s in different files that override the same parameter, the final value of the parameter is indeterminate.

The disadvantages of specifying parameter assignments using defparam are:

The parameter is typically specified by the scope of the hierarchies underneath which it exists. If a particular module gets ungrouped in its hierarchy, [sometimes necessary during synthesis], then the scope to specify the parameter is lost, and is unspecified. B


For example, if a module is instantiated in a simulation testbench, and its internal parameters are then overridden using hierarchical defparam constructs (For example, defparam U1.U_fifo.width = 32;). Later, when this module is synthesized, the internal hierarchy within U1 may no longer exist in the gate-level netlist, depending upon the synthesis strategy chosen. Therefore post-synthesis simulation will fail on the hierarchical defparam override.

Can there be full or partial no-connects to a multi-bit port of a module during its instantiation?

No. There cannot be full or partial no-connects to a multi-bit port of a module during instantiation

What happens to the logic after synthesis, that is driving an unconnected output port that is left open (, that is, noconnect) during its module instantiation?

An unconnected output port in simulation will drive a value, but this value does not propagate to any other logic. In synthesis, the cone of any combinatorial logic that drives the unconnected output will get optimized away during boundary optimisation, that is, optimization by synthesis tools across hierarchical boundaries.

How is the connectivity established in Verilog when connecting wires of different widths?

When connecting wires or ports of different widths, the connections are right-justified, that is, the rightmost bit on the RHS gets connected to the rightmost bit of the LHS and so on, until the MSB of either of the net is reached.

Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?

The width elements of ports, wire or reg declarations require a constant in both MSB and LSB. Before Verilog 2001, it is a syntax error to specify a function call to evaluate the value of these widths. For example, the following code is erroneous before Verilog 2001 version.

reg [ port1(val1:vla2) : port2 (val3:val4)] reg1;

In the above example, get_high and get_low are both function calls of evaluating a constant result for MSB and LSB respectively. However, Verilog-2001 allows the use of a function call to evaluate the MSB or LSB of a width declaration

What is the implication of a combinatorial feedback loops in design testability?

The presence of feedback loops should be avoided at any stage of the design, by periodically checking for it, using the lint or synthesis tools. The presence of the feedback loop causes races and hazards in the design, and 104 RTL Design

leads to unpredictable logic behavior. Since the loops are delay-dependent, they cannot be tested with any ATPG algorithm. Hence, combinatorial loops should be avoided in the logic.

What are the various methods to contain power during RTL coding?

Any switching activity in a CMOS circuit creates a momentary current flow from VDD to GND during logic transition, when both N and P type transistors are ON, and, hence, increases power consumption.


The most common storage element in the designs being the synchronous FF, its output can change whenever its data input toggles, and the clock triggers. Hence, if these two elements can be asserted in a controlled fashion, so that the data is presented to the D input of the FF only when required, and the clock is also triggered only when required, then it will reduce the switching activity, and, automatically the power.

The following bullets summarize a few mechanisms to reduce the power consumption:

Reduce switching of the data input to the Flip-Flops.

Why we do gate level simulations?

Since scan and other test structures are added during and after synthesis, they are not checked by the rtl simulations and therefore need to be verified by gate level simulation.
Static timing analysis tools do not check asynchronous interfaces, so gate level simulation is required to look at the timing of these interfaces.
Careless wildcards in the static timing constraints set false path or mutlicycle path constraints where they don't belong.
Design changes, typos, or misunderstanding of the design can lead to incorrect false paths or multicycle paths in the static timing constraints.
Using create_clock instead of create_generated_clock leads to incorrect static timing between clock domains.
 Gate level simulation can be used to collect switching factor data for power estimation.
X's in RTL simulation can be optimistic or pessimistic. The best way to verify that the design does not have any unintended dependence on initial conditions is to run gate level simulation.
 It's a nice "warm fuzzy" that the design has been implemented correctly.

 Say if I perform Formal Verification say Logical Equivalence across Gatelevel netlists(Synthesis and post routed netlist). Do you still see a reason behind GLS.?

If we have verified the Synthesized netlist functionality is correct when compared to RTL and when we compare the Synthesized netlist versus Post route netlist logical Equivalence then I think we may not require GLS after P & R. But how do we ensure on Timing . To my knowledge Formal Verification Logical Equivalence Check does not perform Timing checks and dont ensure that the design will work on the operating frequency , so still I would go for GLS after post route database.

An AND gate and OR gate are given inputs X & 1 , what is expected output?

AND Gate output will be X
OR Gate output will be 1.

What is difference between NMOS & RNMOS?

RNMOS is resistive NMOS that is in simulation strength will decrease by one unit , please refer to below Diagram.

Tell something about modeling delays in verilog?

Verilog can model delay types within its specification for gates and buffers. Parameters that can be modelled are T_rise, T_fall and T_turnoff. To add further detail, each of the three values can have minimum, typical and maximum values
T_rise, t_fall and t_off


Delay modelling syntax follows a specific discipline;
gate_type #(t_rise, t_fall, t_off) gate_name (paramters);
When specifiying the delays it is not necessary to have all of the delay values specified. However, certain rules are followed.

and #(3) gate1 (out1, in1, in2);
When only 1 delay is specified, the value is used to represent all of the delay types, i.e. in this example, t_rise = t_fall = t_off = 3.


or #(2,3) gate2 (out2, in3, in4);
When two delays are specified, the first value represents the rise time, the second value represents the fall time. Turn off time is presumed to be 0.


buf #(1,2,3) gate3 (out3, enable, in5);
When three delays are specified, the first value represents t_rise, the second value represents t_fall and the last value the turn off time.
Min, typ and max values

The general syntax for min, typ and max delay modelling is;

gate_type #(t_rise_min:t_ris_typ:t_rise_max, t_fall_min:t_fall_typ:t_fall_max, t_off_min:t_off_typ:t_off_max) gate_name (paramteters);


Similar rules apply for th especifying order as above. If only one t_rise value is specified then this value is applied to min, typ and max. If specifying more than one number, then all 3 MUST be scpecified. It is incorrect to specify two values as the compiler does not know which of the parameters the value represents.


An example of specifying two delays;
and #(1:2:3, 4:5:6) gate1 (out1, in1, in2);
This shows all values necessary for rise and fall times and gives values for min, typ and max for both delay types.


Another acceptable alternative would be;
or #(6:3:9, 5) gate2 (out2, in3, in4);
Here, 5 represents min, typ and max for the fall time.


N.B. T_off is only applicable to tri-state logic devices, it does not apply to primitive logic gates because they cannot be turned off.

 

What are conditional path delays?

Conditional path delays, sometimes called state dependent path delays, are used to model delays which are dependent on the values of the signals in the circuit. This type of delay is expressed with an if conditional statement. The operands can be scalar or vector module input or inout ports, locally defined registers or nets, compile time constants (constant numbers or specify block parameters), or any bit-select or part-select of these. The conditional statement can contain any bitwise, logical, concatenation, conditional, or reduction operator. The else construct cannot be used.//Conditional path delays

Draw a 2:1 mux using switches and verilog code for it?

1-bit 2-1 Multiplexer





This circuit assigns the output out to either inputs in1 or in2 depending on the low or high values of ctrl respectively.// Switch-level description of a 1-bit 2-1 multiplexer
// ctrl=0, out=in1; ctrl=1, out=in2

module mux21_sw (out, ctrl, in1, in2);
output out; // mux output
input ctrl, in1, in2; // mux inputs
wire w; // internal wire

inv_sw I1 (w, ctrl); // instantiate inverter module
cmos C1 (out, in1, w, ctrl); // instantiate cmos switches
cmos C2 (out, in2, ctrl, w);

endmodule

An inverter is required in the multiplexer circuit, which is instantiated from the previously defined module.

Two transmission gates, of instance names C1 and C2, are implemented with the cmos statement, in the format cmos [instancename]([output],[input],[nmosgate],[pmosgate]). Again, the instance name is optional.

What are the synthesizable gate level constructs?

The above table gives all the gate level constructs of only the constructs in first two columns are synthesizable.

Reduce the clock switching of the Flip-Flops.
Have area reduction techniques within the chip, since the number of gates/Flip-Flops that toggle can be reduced.

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 Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case?

This is a popular coding error. You used the bit wise AND operator (&) where you meant to use the logical AND operator (&&).

What are Different types of Verilog Simulators ?

There are mainly two types of simulators available.
Event Driven
Cycle Based

Event-based Simulator:

This Digital Logic Simulation method sacrifices performance for rich functionality: every active signal is calculated for every device it propagates through during a clock cycle. Full Event-based simulators support 4-28 states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full timing calculations for all devices; and the full HDL standard. Event-based simulators are like a Swiss Army knife with many different features but none are particularly fast.

Cycle Based Simulator:

This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve huge performance gains in verifying Boolean logic:


1.) Results are only examined at the end of every clock cycle; and

2.) The digital logic is the only part of the design simulated (no timing calculations). By limiting the calculations, Cycle based Simulators can provide huge increases in performance over conventional Event-based simulators.

Cycle based simulators are more like a high speed electric carving knife in comparison because they focus on a subset of the biggest problem: logic verification.

Cycle based simulators are almost invariably used along with Static Timing verifier to compensate for the lost timing information coverage.

What is Constrained-Random Verification ?

As ASIC and system-on-chip (SoC) designs continue to increase in size and complexity, there is an equal or greater increase in the size of the verification effort required to achieve functional coverage goals. This has created a trend in RTL verification techniques to employ constrained-random verification, which shifts the emphasis from hand-authored tests to utilization of compute resources. With the corresponding emergence of faster, more complex bus standards to handle the massive volume of data traffic there has also been a renewed significance for verification IP to speed the time taken to develop advanced testbench environments that include randomization of bus traffic.

Directed-Test Methodology

Building a directed verification environment with a comprehensive set of directed tests is extremely time-consuming and difficult. Since directed tests only cover conditions that have been anticipated by the verification team, they do a poor job of covering corner cases. This can lead to costly re-spins or, worse still, missed market windows.

Traditionally verification IP works in a directed-test environment by acting on specific testbench commands such as read, write or burst to generate transactions for whichever protocol is being tested. This directed traffic is used to verify that an interface behaves as expected in response to valid transactions and error conditions. The drawback is that, in this directed methodology, the task of writing the command code and checking the responses across the full breadth of a protocol is an overwhelming task. The verification team frequently runs out of time before a mandated tape-out date, leading to poorly tested interfaces. However, the bigger issue is that directed tests only test for predicted behavior and it is typically the unforeseen that trips up design teams and leads to extremely costly bugs found in silicon.

Constrained-Random Verification Methodology

The advent of constrained-random verification gives verification engineers an effective method to achieve coverage goals faster and also help find corner-case problems. It shifts the emphasis from writing an enormous number of directed tests to writing a smaller set of constrained-random scenarios that let the compute resources do the work. Coverage goals are achieved not by the sheer weight of manual labor required to hand-write directed tests but by the number of processors that can be utilized to run random seeds. This significantly reduces the time required to achieve the coverage goals.

Scoreboards are used to verify that data has successfully reached its destination, while monitors snoop the interfaces to provide coverage information. New or revised constraints focus verification on the uncovered parts of the design under test. As verification progresses, the simulation tool identifies the best seeds, which are then retained as regression tests to create a set of scenarios, constraints, and seeds that provide high coverage of the design.

Difference between blocking and nonblocking assignments

While both blocking and nonblocking assignments are procedural assignments, they differ in behaviour with respect to simulation and logic

synthesis as follows:

How can I model a bi-directional net with assignments influencing both source and destination?

The assign statement constitutes a continuous assignment. The changes on the RHS of the statement immediately reflect on the LHS net. However, any changes on the LHS don't get reflected on the RHS. For example, in the following statement, changes to the rhs net will update the lhs net, but not vice versa.


System Verilog has introduced a keyword alias, which can be used only on nets to have a two-way assignment. For example, in the following code, any changes to the rhs is reflected to the lh s , and vice versa.
wire rhs , lhs
assign lhs=rhs;

System Verilog has introduced a keyword alias, which can be used only on nets to have a two-way assignment. For example, in the following code, any changes to the rhs is reflected to the lh s , and vice versa.

module test ();
wire rhs,lhs;

alias lhs=rhs;

In the above example, any change to either side of the net gets reflected on the other side.

Are tasks and functions re-entrant, and how are they different from static task and function calls?

In Verilog-95, tasks and functions were not re-entrant. From Verilog version 2001 onwards, the tasks and functions are reentrant. The reentrant tasks have a keyword automatic between the keyword task and the name of the task. The presence of the keyword automatic replicates and allocates the variables within a task dynamically for each task entry during concurrent task calls, i.e., the values don’t get overwritten for each task call. Without the keyword, the variables are allocated statically, which means these variables are shared across different task calls, and can hence get overwritten by each task call.





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How to write FSM is verilog?

There are mainly 4 ways 2 write FSM code
1) using 1 process where all input decoder, present state, and output decoder r combine in one process.
2) using 2 process where all comb ckt and sequential ckt separated in different process
3) using 2 process where input decoder and persent state r combine and output decoder seperated in other process
4) using 3 process where all three, input decoder, present state and output decoder r separated in 3 process.

What is difference between freeze deposit and force?

$deposit(variable, value);

This system task sets a Verilog register or net to the specified value. variable is the register or net to be changed; value is the new value for the register or net. The value remains until there is a subsequent driver transaction or another $deposit task for the same register or net. This system task operates identically to the ModelSim

force -deposit command

The force command has -freeze, -drive, and -deposit options. When none of these is specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved signals. This is designed to provide compatibility with force files. But if you prefer -freeze as the default for both resolved and unresolved signals.

Will case infer priority register if yes how give an example?

yes case can infer priority register depending on coding style reg r;


// Priority encoded mux,

always @ (a or b or c or select2)
begin
r = c;

case (select2)
2'b00: r = a;
2'b01: r = b;

endcase

end

Casex,z difference,which is preferable,why?

CASEZ :
Special version of the case statement which uses a Z logic value to represent don't-care bits. CASEX :
Special version of the case statement which uses Z or X logic values to represent don't-care bits.
CASEZ should be used for case statements with wildcard don’t cares, otherwise use of CASE is required; CASEX should never be used.

This is because:

Don’t cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will automatically match any x or z with anything in the case statement. Casez will only match z’s -- x’s require an absolute match.

Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

a = 0;

#0 a <= 1;
$display(a);
end

This is a tricky one! Verilog scheduling semantics basically imply a, please run this code and get answer: write in the comment section

four-level deep queue for the current simulation time:

1: Active Events (blocking statements)

2: Inactive Events (#0 delays, etc)

3: Non-Blocking Assign Updates (non-blocking statements)

4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.


Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;



#5 a = b; Wait five time units before doing the action for "a = b;".


a = #5 b; The value of b is calculated and stored in an internal temp register,After five time units, assign this stored value to a.

What is the difference between -->

c = foo ? a : b;
and
if (foo) c = a;
else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

What are Intertial and Transport Delays ??

What does `timescale 1 ns/ 1 ps signify in a verilog code?

'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage : `timescale / reference_time_unit : Specifies the unit of measurement for times and delays. time_precision: specifies the precision to which the delays are rounded off.

 What is the difference between === and == ?

output of "==" can be 1, 0 or X.

output of "===" can only be 0 or 1.

When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits as "x" then the output would be "X" . But if use "===" outpout would be 0 or 1.

e.g A = 3'b1x0

B = 3'b10x

A == B will give X as output.

A === B will give 0 as output.

"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the input is X output will be X

"===" is used for comparison of X also.

How to generate sine wav using verilog coding style?

A: The easiest and efficient way to generate sine wave is using CORDIC Algorithm.

 What is the difference between wire and reg?

Net types: (wire,tri)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a-&gt;b, if there is no connection in a and b, wire loose value. But reg can hold the value even if there in no connection. Default values:wire is Z,reg is x.

How do you implement the bi-directional ports in Verilog HDL?

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

input oe;

input clk;

input [7:0] inp;

output [7:0] outp;

inout [7:0] bidir;

reg [7:0] a;

reg [7:0] b;

assign bidir = oe ? a : 8'bZ ;

assign outp = b;

// Always Construct

always @ (posedge clk)

begin

b <= bidir;

a<= inp;

end

endmodule

what is verilog case (1) ?

wire [3:0] x;

always @(...) begin

case (1'b1)

x[0]: SOMETHING1;

x[1]: SOMETHING2;

x[2]: SOMETHING3;

x[3]: SOMETHING4;

endcase

end

The case statement walks down the list of cases and executes the first one that matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement that will get executed (or selected by the logic).

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physical design interview2

Explain the flow of physical design and inputs and outputs for each step in flow.

The physical design flow is generally explained in the Figure

 (1.). In each section of the flow EDA tools available from the two main EDA companies-Synopsys and Cadence is also listed. In each and every step of the flow timing and power analysis can be carried out. If timing and power requirements are not met then either the whole flow has to be re-exercised or going back one or two steps and optimizing the design or incremental optimization may meet the requirements

What is cell delay and net delay?

Gate delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

Gate delay =function of(i/p transition time, Cnet+Cpin).

Cell delay is also same as Gate delay.

Cell delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

Intrinsic delay

Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

Wire delay =fn(Rnet , Cnet+Cpin)

What are delay models and what is the difference between them?

1. Linear Delay Model (LDM)
2. Non Linear Delay Model (NLDM)

What is wire load model?

Wire load model is NLDM which has estimated R and C of the net.

Why higher metal layers are preferred for Vdd and Vss?

1. Because it has less resistance and hence leads to less IR drop.

What is logic optimization and give some methods of logic optimization.

1. Upsizing
2. Downsizing
3. Buffer insertion
4. Buffer relocation
5. Dummy buffer placement

What is the significance of negative slack?

1. negative slack==&gt; there is setup voilation==&gt; deisgn can fail

What is signal integrity? How it affects Timing?

1. IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.
2. If Idrop is more==&gt;delay increases.
3. crosstalk==&gt;there can be setup as well as hold voilation.

What is IR drop? How to avoid? How it affects timing?

1. There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.
2. If IR drop is more==&gt;delay increases.

What is EM and it effects?

1. Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.
3. Affects: Either short or open of the signal line or power line.

What are types of routing?

1. Global Routing
2. Track Assignment
3. Detail Routing

What is latency? Give the types?

Source Latency

1. It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".
3. Delay from clock source to beginning of clock tree (i.e. clock definition point).
5. The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network latency

1. It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".
3. The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is track assignment?

1. Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

What is congestion?

1. If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

Whether congestion is related to placement or routing?

1. Routing

What are clock trees?

1. Distribution of clock from the clock source to the sync pin of the registers.

What are clock tree types?

1. H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is cloning and buffering?

1. Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
2. Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy

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physical design interview1

What parameters (or aspects) differentiate Chip Design and Block level design?

1. Chip design has I/O pads; block design has pins.
2. Chip design uses all metal layes available; block design may not use all metal layers.
3. Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
4. Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design?

1. First check fly lines i.e. check net connections from macro to macro and macro to standard cells.
2. If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.
3. If input pin is connected to macro better to place nearer to that pin or pad.
4. If macro has more connection to standard cells spread the macros inside core.
5. Avoid criscross placement of macros.
6. Use soft or hard blockages to guide placement engine.

Differentiate between a Hierarchical Design and flat design?

1. Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.
2. Hierarchical design takes more run time; Flattened design takes less run time.

Which is more complicated when u have a 48 MHz and 500 MHz clock design?

1. 500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

Name few tools which you used for physical verification?

1. Herculis from Synopsys, Caliber from Mentor Graphics.

What are the input files will you give for primetime correlation?

1. Netlist, Technology library, Constraints, SPEF or SDF file.

If the routing congestion exists between two macros, then what will you do?

1. Provide soft or hard blockage

How will you decide the die size?

1. By checking the total area of the design you can decide die size.

If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?

1. Poly

If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

1. Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

In your project what is die size, number of metal layers, technology, foundry, number of clocks?

1. Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!
2. Metal layers: See your tech file. generally for 90nm it is 7 to 9.
3. Technology: Again look into tech files.
4. Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc
5. Clocks: Look into your design and SDC file !

How many macros in your design?

1. You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

What is each macro size and number of standard cell count?

1. Depends on your design.

What are the input needs for your design?

1. For synthesis: RTL, Technology library, Standard cell library, Constraints
2. For Physical design: Netlist, Technology library, Constraints, Standard cell library

What is SDC constraint file contains?

1. Clock definitions
2. Timing exception-multicycle path, false path
3. Input and Output delays

How did you do power planning?

How to calculate core ring width, macro ring width and strap or trunk width?
How to find number of power pad and IO power pads?
How the width of metal and number of straps calculated for power and ground?

1. Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.
2. How to find total chip power?
3. Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

What are the problems faced related to timing?

1. Prelayout: Setup, Max transition, max capacitance
2. Post layout: Hold

How did you resolve the setup and hold problem?

1. Setup: upsize the cells
2. Hold: insert buffers

In which layer do you prefer for clock routing and why?

Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

If in your design has reset pin, then it’ll affect input pin or output pin or both?

Output pin.

During power analysis, if you are facing IR drop problem, then how did you avoid?

1. Increase power metal layer width.
2. Go for higher metal layer.
3. Spread macros or standard cells.
4. Provide more straps.

Define antenna problem and how did you resolve these problem?

1. Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.
2. Decrease the length of the net by providing more vias and layer jumping.
3. Insert antenna diode.

How delays vary with different PVT conditions? Show the graph.

1. P increase--> dealy increase
2. P decrease--> delay decrease
3. V increase--> delay decrease
4. V decrease--> delay increase
5. T increase--> delay increase
6. T decrease--> delay decrease

Learn More ==>
Physical design part1
Physical design part2
Physical design part3
Placement

verilog interview question part1
verilog interview question part2
verilog interview question part3

All Flip Flop (RS,JK,D,T FF)

--> Below is the detail explanation with dig

: 

PCB-Package-Die Chip flow

Package level

 SOC total pin counts surpassing 30,000
• IO pad-ring generation no longer a simple task.
• Staggered, multi-row placement
• Area IO placement
• Flip-chip development
• Managing, placing and optimizing bumps
• RDL routing
• High Speed serial I/Os
• I/O buffer scaling for minimum power
• Interconnect modeling across package and PCB
• Power delivery across PCB, Package and IC
• Trade off analysis between wire bond and flip-chip
• More accurate 3D (full-wave) analysis for package and PCB interconnect structures
• Package costs killing profit margin
• Drive to standard packages
• Package selection no longer an afterthought
• PCB layout is a bottle-neck to volume
• Interconnect/Routing problems on the PCB are amplified by the high pin count devices.
• Additional layers driving up cost

IC level

• I/Os
• Peripheral (including multi-row stagger)
• Area (including direct bumping)
• Bumps (C4s)
• Interposer
• Package level
• Bumps (C4s)
• Bond fingers
• Package pins
• Interposers
• PCB level
• Package pins (including breakouts)

Physical Design Routing Process : VLSI chip metal routing

1. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. 
2. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. 
3. The connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. 
4. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. 
5. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. 
6. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.

 Routing create physical connections  to all the data signal if clock nets are already routed after clock tree optimization.

There are 3 stages in routing
(i)GLOBAL ROUTING
(ii)TRACK ASSIGNMENT
(iii)DETAIL ROUTING

Global Routing:

First the design is divided into small boxes every box is called global routing cells (gcells or buckets)

every gcell having the a number of horizontal routing resources and vertical routing resources.

global routing assigns nets(logical connectivity not metal connectivity) to spacific metal layers and global routing cells.

By using global routing we can analyze congestion.

Congestion =(required routing resources > available routing resources)

If any gcell have congestion then detouring(avoid the gcell routing through another gcell).

Track Assignments :

Assigns each net to the spacific tracks.

Nets are laydown the metal traces.

Traces=metal connectivity.

 

Detail Routing:

Detail route dones actual routing. means actual routing metal connections. it checks also physical drc's.

Detail routing does not work on the entire chip at the same time like track assignment, instead it works be rerouting within the confines of a small area called an "sbox".

sbox : divide the block into mini boxes these are used for the detail route.

Grid based and gridless routing:

 In grid based routing, a routing grid is superimposed on routing region. Routing takes place along the grid lines. The space between adjacent grid lines is called wire pitch and is equal to sum of minimum width of wires and spacing of wires. On the other hand, any model that does not follow grid based routing is termed as gridless routing model. This model is suitable for wire sizing and perturbation and is more complex and slower than grid based routing. In other words, grid based routing is much easier and simpler in implementation. We have discussed here routing in VLSI designs. Although many advanced tools are available for achieving the purpose, most of these compromise with the quality of results to save run-time. Almost all tools have the option of routing with more emphasis on meeting timing or congestion. With most of the tools, in present day multi-million gate designs, perfect DRC-free routing (without opens and shorts) is generally not obtained in first pass. You have to route incrementally a few times to achieve the same.