Verifying the Power Network Definition : check_mv_design

•  To verify the power network definition for a multivoltage design, run the check_mv_design command. 
• This command checks for various types of violations such as inconsistent and conflicting library settings, missing isolation cells, and incorrect voltage shifting across power domains. •
• To check the power and ground connections, use the -power_connectivity option.
•  When you use this option, the tool checks the power and ground connections in addition to the power network definition, and updates the connections if it finds any issues. By default, it does not check the power and ground connections. 
• To specify the maximum number of messages for each violation type, use the -max_message_count option. By default, it reports a only 20 occurrences of a given violation type

# Procedure in ICC Apply the UPF

 load_upf $upf_input_file_name

## Common command used in UPF 

• create_supply_port
• create_supply_net
• create_power_switch
• connect_supply_net
• create_power_domain
• set_isolation
• set_level_shifter
• set_retention
• add_port_state create_pst add_ast_state .. et

 commit_upf … … 

# create logical supply nets set_app_options -as_user_default \ -list {mv.pg.create_floating_pg true} connect_pg_net –automatic 

check_mv_design

CLP low power checks

 Once we start working on low power design, we need to perform low power checks 

That includes 

    Reading the PG netlist 

    Reading the UPF

    Run low power checks called CLP

Make sure IN ICC your check_mv_design is clean

Types of low  power checks

      Static Checks  

      Dynamic checks : Dynamic checks are performed on the design while running simulation. Dynamic checks detect behavioral issues in the design, such as incorrect power sequencing of power domains

Isolation cells

Lets look into the below picture , where we have two power domains PD1 & PD2. 

There is a signal crossing from PD1 to PD2.

When the chip is in functional working mode, when all the power domains are up -> 

Signal s1 will be  either a 0 or 1 value.

Now when the  PD_1 is powered-off and PD_2 is powered-ON.

    The value of signal s1 is unknown. That will corrupt the powered-up logic in the PD_2 domain

This is the condition where we need to insert isolation cells to avoid corrupting the signal S1. 

When we run CLP, tool will flag the below errors.

Clp-report-isolation-check

Level Shifter

Consider the scenario when  both of the power domains are powered-up. 

Now if voltage difference between the power domains is less than a threshold value, or means both the domains are working at equal voltage. then  there are no issues in the design. 

 if the voltage difference is greater than the threshold value, means PD3 is 1.5v & PD4 is 0.85, then a logic 1 at PD_1 can be assumed a logic 0 at PD_2. This leads to incorrect data transmission.

TO avoid this condition we need a level shifter cell. 

A level shifter cell can be of the following two types:

• High-to-Low – Converts a high-voltage level to a low-voltage level. It is inserted when the source power domain operates at a higher voltage and the sink power domain operates at a lower voltage.
• Low-to-High – Converts a low-voltage level to a high-voltage level. It is inserted when the source power domain operates at a lower voltage and the sink power domain operates at a higher voltage.

clp Level shifter checks: report

Retention cells  &    Checks

Consider you have a power domain, which is powered-down. When the domain is powered-up again, all the state information from before the domain was powered-down is lost. To avoid this, designers place retention cells in power domains, which stores the state value of the power domain. Retaining the state value helps the power domain become operational sooner.

A design may have multiple power domains that are powered-down, which may lead to many retention issues. The simulator runs various retention checks on the design to find out the retention issues, and flags an error in case of a violation.

Back-to-Back Checks

• Sometimes your design has back-to-back cells, which might be any of the following types:
• Isolation and level shifter cell
• Level shifter and isolation cell
• Isolation and isolation cell
• Level shifter and level shifter cell

Other checks

• The design cells have missing liberty attributes.
• The isolation, level shifter, or retention supply is powered-down during the active isolation, level shifting, or retention period.
• The power signal of a power domain gets corrupted.
• The input of a power domain toggles when the power domain is powered-down.
• The power state table or the supply port reaches an illegal or undefined state.

https://www.powerelectronictips.com

CLP retention cells checks

• A retention cell is required, but it is neither present in the design nor specified in the UPF file.
• A retention cell is not required (as the power domain is an always-on domain), but it is either present in the design or specified in the UPF file.
• A retention cell is present in the design, but it does not have the corresponding strategy defined in the UPF file.
• A retention strategy is specified in the UPF file, but a retention cell is not present in the design.
• The retention condition is not asserted when the power domain is powered-down.
• The retention control signal is not generated from an always-on domain, or is unconnected, or is driven by a constant.
• The retention condition is disabled at power down or power up.
• The retention condition toggles at power down.

Retention cells

These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.

 All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/place/route them. 

In a nut-shell, “When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”.

The retention flop has the same structure as a standard master-slave flop. 

However, the retention flop has a balloon latch that is connected to true-Vdd. 

With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch.

 Similarly, when the block comes out of sleep, the data can be written back into the flip-flop

CLP Static checks

• Static checks detect architectural issues in the design.
• As a missing isolation or level shifter cell.
• Can be performed without running a simulation
• Save time and effort as you do not need to write a testbench. So you can run them on your low-power design as soon as the design is readyThere are two kinds of static checks: static RTL and static gate-level simulation (GLS) checks. The static RTL checks are run on RTL designs and static GLS checks on gate-level design

Level Shifter Cells

Level Shifters (LS) are special standard cells used in Multi Voltage designs to covert one voltage level to another. 

As Multi Voltage designs have more than one voltage domain, level shifters are used for all the signals crossing from one voltage domain to another voltage domain. 

Like isolation cells, level shifters are inserted by the synthesis tool

Low to High Level Shifters

Low to High LS are used for signals crossing from a lower voltage domain to higher voltage domain.

It basically amplifies the source signal so that it can be interpreted properly in the destination domain. 

Suppose a 0.7V signal is crossing from 0.7V voltage domain to 1.0V voltage domain. Now in the lower voltage domain it corresponds to logic-1 but in higher voltage domain it is neither logic-1 nor logic-0, so the signal becomes unknown (or ‘X’) in the absence of Low to High LS.

High to Low Level Shifters

High to Low LS are used for signals crossing from higher voltage domain to lower voltage domain.
It basically attenuates the source signal. 

Although putting a LS for signals crossing from higher voltage domain to lower voltage domain is optional as signals will be interpreted properly in destination domain, but typically we put a LS to avoid stress on the transistors of lower voltage domain due to high voltage of the source signal.

Bi-directional Level Shifters

When dynamic voltage scaling or dynamic voltage freq scaling is used the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high voltage signals and high to low voltage signals.

CLP Report Level Shifter Checks

A few cases when the simulator flags an error are listed below:

• A level shifter cell is required for a crossing, but it is neither present in the design nor specified in the UPF file.
• A level shifter cell is not required for a crossing, but it is either present in the design or specified in the UPF file.
• A level shifter cell is present in the design, but the corresponding strategy is not defined in the UPF file.
• A level shifter strategy is specified in the UPF file, but a level shifter cell is not present in the design.
• The direction of the level shifter cell specified in the UPF file is not correct. For example, instead of a high-to-low level shifter cell, a low-to-high level shifter cell is specified.
• The location of the level shifter cell does not match with the location specified in the UPF file.

CLP Report ISOLATION CHECKS

• An isolation cell is required for a crossing, but it is neither present in the design nor specified in the UPF file.
• An isolation cell is not required for a crossing, but it is either present in the design or specified in the UPF file.
• An isolation cell is present in the design, but the corresponding strategy is not defined in the UPF file.
• An isolation strategy is specified in the UPF file, but an isolation cell is not present in the design.
• Two different clamp values are specified for an isolation cell in the UPF file.
• The isolation clamp value is different from the reset value of the flop.
• The clamp value of the isolation cell in the design does not match the corresponding strategy specified in the UPF file.
• The location of the isolation cell in the design does not match the location specified in the UPF file.
• The isolation control signal is not generated from an always-on region, or is unconnected, floating, or driven by constants.
• The isolation enable signal specified in the UPF file reaches the data pin of the isolation cell or does not reach the enable pin of the isolation cell.
• For an internally isolated IP pin, an isolation cell is present in the design or is specified in the UPF file.
• The isolation control signal is disabled when the source domain is powered-down and the sink domain is powered-up or when the source domain is in a CORRUPT state and the sink domain is not in a CORRPUT state.
• The isolation control signal is active when there is no requirement for isolation.
• The value at the output of an isolation cell is different from that at its input during normal working conditions.
• The value of the isolated port changes during the active isolation period.

isolation cell

Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain. 

They clamp the output node to a known voltage.

In the isolation list we specify the clamping value of the nets as logic 0 or logic 1 and accordingly the synthesis tool will insert isolation cells.