Design Flow IO of ASIC flow: Physical design flow

Library Preparation

Inputs required:

– Logical information of standard cells
– Physical Information of standard cells
– Technology rules

Outputs:

– Library Milkway database
– .CEL view

Synthesis

Inputs required:

– RTL (.v or .vhdl)
– Timing constraints (.sdc or .tcl)

-.libs 

-def if running DC-topo

Outputs:

– Netlist (.v) 

Design Preparation 

Inputs required:

- Netlist
- Reference lib

Outputs:

-Milkyway database

Floorplan

Inputs required:

– Synthesized Netlist
– Physical Information of your design ( Rules for targeted technology)
– Floorplan parameters (like height, width,utilization etc.)
– Pin/Pad position

Outputs:

– Design bonded with technology with specified area, macro placement and fixed pin placement
once floorplan is over u need to check

Powerplan

-Inputs required:

– Data base with floorplan information
– Width of power rings, power straps
– Spacing between pair of VDD & VSS straps
– Spacing between VDD and VSS strap

Output:

– Design with power structure

Placement

Inputs required:

– Data base with floorplan and powerplan information
– Timing Constraints

Outputs:

– Data base with legalization placement of standard cells
– Timing reports
– Congestion Statistics

Clock Tree Synthesis

Inputs required:

– Detail placement and timing optimized database
– Target for Latency and skew
– Buffers that needs to be used for building up clock tree

Outputs:

– Legally placed Data base with Clock tree
– Timing reports
– Clock tree report
– Skew report
 

CTS TARGETS :  Minimum latency and minimized skew
 Others:

(i)max transition,  

(ii)max capacitance,
(iii)max fanout,
(iv)max buffer levels

Routing

Inputs required:

– Legally placed database with clock tree structure

Outputs:

– Detailed routed database with no opens and shorts (expected)