Reading in the design: Logic synthesis

The first task in synthesis is to read the design into Design Compiler memory. Reading in an HDL design description consist of two tasks: 

• Analyzing and elaborating the description. 
• The analysis command (analyze) performs the following tasks:  

1. Reads the HDL source and checks it for syntactical errors 
2. Creates HDL library objects in an HDL-independent intermediate format and saves these intermediate files in a specified location

Debug: If the analysis reports errors, they must be fixed, and the design reanalyzed before continuing. 

The elaboration command (elaborate) does  the following:

1. GTECH netlist: Translates the design into a technology-independent design from the intermediate files produced during analysis 
2. Allows changing of parameter values (generics) defined in the source code 
3. Replaces the HDL arithmetic operators in the code with DesignWare components 
4. Automatically executes the link command, which resolves design references 

Debug: you need to  check the elaboration reports carefully to check the number and the type of memory elements Design Compiler thinks it should infer and whether you agree with it or not. Badly modeled hardware description may result as excessive or wrong type of memory elements inferred.  Now, if the elaboration completed successfully, the design is represented in GTECH format: 

 which is an internal, equation-based, technology-independent design format. 

Physics of Power

Dynamic power -> 

Switching Power: is the Power spent ->

Charging and discharging the capacitance of the output net: called load power or CV2 power. Switching power is a function of switching activity and load capacitance, it is data dependent

Short Circuit Power:  is the Power dissipated -> 

Inside the gate when switching, also known as internal power or crowbar power

Total of internal power and switching power called dynamic power

Static Power: is the power when: 

No signals are changing values; means when device is not functional; means the Leakage Power or is a calculation of leakage power called static power

IR Drop: 

Dynamic IR Drop: Dependent on the switching activity of the standard cells themselves.  

                                             Vdynamic_drop = L (di/dt)

1. (RC)max corner -> RCWorst corner. PVT Conditions -> impact of the standard cells. Highest switching activity for standard cells --> ff corner High V & High T  High T > More resistance -> more RC

Static IR drop:  Vstatic_drop = Iavg x Rwire 

Depends on the RC of the power grid connecting the power supply to the respective standard cells

R-> Higher metal layers ->  wide wires -> lower resistance -> low IR drop -> lesser  impact on setup-timing. 

C-> Capacitance of metal wires ->  combination of ground and the coupling capacitance -> if  capacitance is too large -> More IR drop:: 

            Long wire length               - >  Higher wire cap.

            High fan-out of the net       ->  Higher load-cap

            High routing congestion      -> Higher coupling capacitance 

Rectilinear to rectangle script ICC

proc rectlinear2rectangles {rectilinear_boundary} {
set rects [split_polygons -objects [create_poly_rect -boundary $rectilinear_boundary] -output poly_rect]
set count 1

foreach bbox [get_attribute $rects bbox] {
set section$count $bbox
puts "section$count = $bbox"
incr count
  }
}

Now implement like:
rectlinear2rectangles  [get_attr [get_sel] boundary] ]
Reference : icc2