Aspect Ratio of Core/Block/Design

The Aspect Ratio of Core/Block/Design is given as:

The aspect ratios of different core shapes are given in below :

The Role of Aspect Ratio on the Design:

1. The aspect ratio effects the routing resources available in the design
2. The aspect ratio effects the congestion
3. The floorplanning need to be done depend on the aspect ratio
4. The placement of the standard cells also effect due to aspect ratio
5. The timing and there by the frequency of the chip also effects due to aspect ratio
6. The clock tree build on the chip also effect due to aspect ratio
7. The placement of the IO pads on the IO area also effects due to aspect ratio
8. The packaging also effects due to the aspect ratio
9. The placement of the chip on the board also effects
10. Ultimately every thing depends on the aspect ration of core/block/design
    

Standard Cell Rows

The area allotted for standard cells on the core is known as standard cell area. This area is divided into the rows known as standard cell rows as shown in the below figure

The height of this row is equal to the height of the standard cell. In digital designs most of the cases, the height of standard cells are constant and width varies. There may be double height cells , triple height cell, etc. Similarly the rows also have heights accordingly. The standard cells will sit in the row with proper orientation.
The rows may abut or may not. The abutted rows share the power connections

Min Pulse Width Violation

Min pulse width check is to ensure that pulse width of clock signal is more than required value.


Basically it is based on frequency of operation and Technology. Means if frequency of design is 1Ghz than typical value of each high and low pulse width will be equal to (1ns/2) 0.5ns if duty cycle is 50%.


Normally we see that in most of design duty cycle always keep 50% otherwise designer can face issues like clock distortion and if in our design using half cycle path means data launch at +ve edge and capturing at -ve edge and again min pulse width as rise level and fall level will not be same and if lots of buffer and inverter will be in chain than it is possible that pulse can be completely vanish.


Also we have to consider the best and worst case when clock get routed and depend on that decide that what should be the required value of Min Pulse Width.


Now we know that rise delay and fall delay of combinational cells are not equal so if a clock entering in a buffer than the output of clock pulse width will be separate to input.
So for example, if buffer rise delay is more than fall delay than output of clock pulse width for high level will be less than input.





so,
High pulse : 0.5-0.056+ 0.049 = 0.493 &
Low pulse : 0.5-0.049+0.056 = 0.507


For better understanding we go with real time scenario for Min Pulse Width.


Normally for clock path we use clock buffer because of the equal rise delay and fall delay of these buffer compare to normal buffer but this delay is not exact equal thatswhy we have to check min pulse width.


We can understand it with an example :-


Lets there is a clock signal which is going to clock pin of flop through series of buffers with different rise and fall delay. we can calculate that how it effect to high or low pulse of clock.

we can understand through calculation:-


High pulse width = 0.5 + (0.049 - 0.056) + (0.034 – 0.039) + (0.023 – 0.026) + (0.042 – 0.046) + (0.061 – 0.061) + (0.051 – 0.054) = 0.478ns

Low Pulse width = 0.5 + (0.056 – 0.049) + (0.038 – 0.034) + (0.026 – 0.023) + (0.046 – 0.042) + (0.061 – 0.061) + (0.054 – 0.051) = 0.522ns



Lets required value of Min pulse width is 0.420ns.

Uncertainty = 80ps
than high pulse width = 0.478-0.080 = 0.398ns
Now we can see that we are getting violation for high pulse as total high pulse width is less than Require value.

Solution

So for solving this violation we can add an inverter which will change the transition and improve it.
as for the the first inverter high pulse will be more then low &  in the next  vice versa.