A tie-high, tie-low circuit

Tie-high and tie-lo cells are used to avoid direct gate connection to the power or ground network. In your design, some cell inputs may require a logic0 or logic1 value. The spare cell inputs are also connected to ground or power nets, as you cannot leave them unconnected. Instead of connecting these to the VDD/VSS rails/rings, you connect them to special cells available in your library called TIE cells.(Note: All libraries may not have them).

A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage.

An integrated circuit (IC) application does not always require all of its inputs to be used. The inputs that are not used should advantageously be locked in a single, stable logic state, and should not be left floating, because inputs having unpredictable or intermediate logic states may have unpredictable and unrepeatable influences on logic outcomes. This is a major issue that IC designers strive to eliminate.



For stability, therefore, small circuits are inserted into ICs. The small circuits have at least two outputs: one that is always high and another that is always low. These circuits are then used to tie IC inputs to either a high state or a low state. By implementing these circuits, inputs that are not used are locked in a single, stable logic state.



However, various issues exist in the conventional designs of these circuits. For example, many of these circuits comprise at least four transistors, which take up valuable real estate in ICs and may require additional, costly production steps. As another example, some of the designs of these circuits comprise three transistors, but such designs typically exhibit limited tolerance to electrostatic discharge (ESD).

Therefore, desirable in the art of integrated circuit designs are improved designs with smaller circuits having increased ESD tolerance that can be used to tie-high or tie-low an unused IC input.

Why do you use them?

Gate oxide is thin and sensitive to voltage surges. Some processes does not let you connect the gates directly to power rails since any surge in voltage, like an ESD event, can damage the gate oxide. Hence tie cells, which are diode connected n-type or p-type devices are used instead.The gates won’t be connected to either power or ground directly.

That is the argument the foundries have for ESD protection against surges. Now, go check the schematic of the TIE cells in your standard cell library.. It is possible that it is just an inverter tied with input tied either to VDD(Ti-lo) or VSS (ti-high). In that case, the gate of the tie cell is still connected to power rails. However there are some uses for these types of cells. Leakage current is reduced in this configuration.Also,rewiring these in times of an ECO is easier, especially if you just want to swap 1’b1 for a 1’b0

Terminology in VLSI

ASIC

Acronym for Application Specific Integrated Circuits. A custom or semi
custom integrated circuit, such as a cell or gate array, created for a specific
application. The complexity of ASICs typically requires significant use of
CAD techniques.

Block

 Also known as functional block or module. Any block within the design
hierarchy instantiated one or more times that will be laid out separately is
referred to as a block module. Block modules are defined divisions of a chip
based on functionality and can be worked on independently of other
functional blocks.

Netlist

 A description of the circuit. The description can be a gate-level or RegisterTransfer
level (RTL) one. It can also be in different languages like Verilog
or VHDL or SPICE.

Physical Design

A portion of a chip or circuit corresponding to a block module that is laid
out separately using a Physical Design tool. It is also referred to as a
physical block, layout region, or layout block.

RTL

 Acronym for Register Transfer Level
Characterization Electrical analysis performed for the purpose of determining typical device
performance characteristics and/or parametric limits.25

CMOS

 Acronym for Complimentary Metal Oxide Semiconductor. An MOS
technology in which both P-channel and N-channel devices are fabricated
on the same die.

Die

 A single square or rectangular piece of silicon into which a specific
semiconductor circuit has been diffused.

Electromigration

 Particle migration in aluminum or copper thin-film or polysilicon
conductors at grain boundaries as a result of high current densities.
Electromigration can lead to either an open circuit condition in a conductor
or a short between adjacent connectors.

Interconnect

The metallization connecting two or more active elements on the surface of
a die; also, the wires connecting the die to the package leads.

Timing Window

Timing window specifies the interval of each circuit node at which a
transition activity is anticipated. For a single clock domain, the time interval
can lie within a clock period. There can be more than one intervals or
overlapping intervals based on complexity of path converging to the node.