Level Shifter in VLSI Chip Design

Level Shifter cell is used to shift a signal voltage range from one voltage domain to another. This is required when the chip is operating at multiple voltage domains. A signal in one voltage domain may have a voltage range which is different to the signal in another voltage domain. This difference in the voltage range may cause unreliable functioning of the destination domain. Hence Level shifter cells are inserted in the voltage domain crossings.



In the picture above the signal from the 0.7V domain drives a logic cell operating in the 1V volatge domain. The 0.7 V domain spends more time in the threshold voltage of the 1V voltage logic cell which may cause unacceptable timing delays and crowbar currents. If the voltage difference is bigger it may happen that the lower voltage range signal may not even get to the threshold voltage of the higher voltage domain logic cell. A level shifter cell in the voltage domain crossover ensures a reliable functioning of the multi-voltage domain chip.

There are two possible situations, one where the source signal voltage is low compared to the sink voltage domain, second one is vice verse. But there can be also situations where dynamic voltage scaling is used and the voltage relation between the source and destination might change over time of operation. In that case we need level shifter which is capable of shifting both low to high and high to low. Accordingly the three types of level shifters are,



Low to High Level ShifterHigh to Low Level ShifterBoth Low to High and High to Low Level Shifter


Low to High Level Shifters can be realized using a buffer or a pair of inverters. The gate voltage of a MOS transistor can be driven up to its breakdown voltage. Breakdown voltage is the voltage beyond which the dielectric gets damaged irreversibly and no longer exhibits the desired dielectric characteristics. This breakdown voltage is typically much higher than the supply voltage. This means the input of the MOS transistor can be driven with an higher voltage than the supply voltage (provided gate voltage is bellow its breakdown voltage).



In the picture shown above the positive gate voltage when it exceeds the Breakdown voltage the dielectric breaks and starts conducting. This is because the dielectric was unable to withstand the voltage stress after a certain voltage level. So a buffer can be used as High to Low Level Shifter if the High voltage signal does not reach its breakdown voltage.



Low to High Level shifter requires a careful transistor sizing. A low voltage signal may not even reach the threshold voltage of the logic cell in the High voltage domain. In this case the level shifter circuit is built by choosing the transistor sizing to bring the threshold voltage down so that the low voltage signal can turn it ON. Also they may increase the GATE thickness to help accumulate the charge better. Traditional Low to High Level Shifter circuit used a cross coupled transistor to amplify the low voltage signal. It consumes more power and introduces more delay. However the designers have come up with many different and efficient ways to implement the Low to High Level Shifter. The circuit implementation of a typical Low to High Level Sifter is show in the picture below.



In the circuit shown above, the P1, P2, N1 and N2 form a cross coupled amplifier which is driven by the low voltage input signal. The transistor size of P1, P2, N1 and N2 are chosen such that the Level Shifter circuit operates reliably for the desired input and output voltage levels. The same circuit can be used for High to Low conversion also. Again the High voltage domain signal should not exceed the gate breakdown voltage. The Level Shifter cell is characterized in all the possible voltages of input and supply and a reliable operating range is derived.

power switch in VLSI Chip

A power switch is used to implement the power gating for a power domain. Power switch that we create in UPF is an abstract model of the actual power switch network which will be implemented in the silicon. For example in coarse grain power gating many parallel power switches are used to implement the power gating. Creating the power switch in UPF serves two purposes. One it captures the power intent of the designer and two it can be used for low power verification.

power_switch

In UPF, a power switch can be created by using the create_power_switch command. The following command creates a power switch for the example in figure.

create_power_switch PDA_SWITCH

-domain PDA

-input_power_port {Vin VDD}

-control_port {Cin SLEEP}

-output_power_port {Vout VDD_GATED}

-ack_port {Aout ACK !SLEEP}

-ack_delay {Aout 100ns}

-on_state {PDA_ON VDD !SLEEP}

-off_state {PDA_OFF SLEEP}

Options input_power_port, control_port and output_power_port does the port mapping for the power switch. Where as option domain specifies the power domain in which the power switch is created. This domain option is synopsys specific but not actually specified in IEEE 1801 standard. While other options like on_state, off_state, ack_port and ack_delay are used to model the power switch. The syntax of which are shown below,

-ack_port {port_name net_name {boolean_function}}

-ack_delay {port_name delay}

-on_state {state_name input_supply_port {boolean_function}}

-off_state {state_name {boolean_function}}

These are required for low power verification. Another model of power switch internally have two separate switches one small and other large (also called mother daughter). Smaller switch is used during the power up. Once the circuit gets to certain voltage level the larger switch is turned ON for normal operation of the power domain logic cells. So two control signals are used for creating these type of power switches.

create_power_switch PDA_SWITCH

-domain PDA

-input_power_port {Vin VDD}

-control_port {CSin SLEEP1}

-control_port {CLin SLEEP2}

-output_power_port {Vout VDD_GATED}

-ack_port {Aout ACK {!SLEEP1 & SLEEP2}}

-ack_delay {Aout 100ns}

-on_state {PDA_ON VDD !SLEEP2}

-off_state {PDA_OFF SLEEP2}

Similarly many different models of power switch can be specified. Apart from the two types of power switches some examples of different types of switches are

Muxed switch: This type of power switch can function as a mux between two input power supplies which can be from different source or of different voltage. One control switch is used to control which of the two supplies are to be selected. Another control signal is used to gate the output supply.

Overlapping Muxed switch: This type of power switch can do a smooth switch over from one supply input to another. This is done by selecting both the supplies at the same time and switching off one after some time during the transition. The two input supplies can be from different source and may have different supply voltages also but they should have the same voltage during the transition. So two control signals for mux select and one control signal to gate the output supply are required.

Mapping power switch:

The supply nets specified in the create_power_switch should already exist in the design. Since the tool has to use a library cell to implement the power switch the designer can specify the library cell that should be used for the purpose by using map_power_switch command. An example is shown bellow,

map_power_switch PDA_SWITCH

-domain PDA

-lib_cells mvlib/headswitch

We must note that the domain specified in both create_power_switch and map_power_switch is the domain in which the power switch is to be placed.

Unconstrainted points with check_timing Command

To check for constraint problems such as undefined clocking, undefined input arrival times, and undefined output constraints, use the check_timing command

pt_shell> check_timing

Information: Checking 'no_clock'.
Warning: There are 4 register clock pins with no clock.
Information: Checking 'no_input_delay'.
Information: Checking 'unconstrained_endpoints'.
Information: Checking 'generic'.
Information: Checking 'latch_fanout'.
Warning: There are 2 level-sensitive latches which fanout to
themselves.
Information: Checking 'loops'.
Warning: There are 6 timing loops in the design.
Information: Checking 'generated_clocks'.

Note: If timing paths are unconstrained, the check_timing command only reports the unconstrained endpoints, not the unconstrained startpoints. Similarly, for paths constrained only by set_max_delay, set_min_delay, or both rather than set_input_delay and set_output_delay, the check_timing command only reports any unconstrained endpoints, not unconstrained startpoints.

To check for unconstrained endpoints use:
report_timing -exceptions

reference solvnet

STA - static timing reports

Global Timing Summary Report

Path Timing Report

Quality of Results Report

Constraint Reports

Bottleneck Report

Global Slack Report

Analysis Coverage Report

Clock Network Timing Report

Clock-Gating and Recovery/Removal Checks

Timing Update Efficiency

Path-Based Timing Analysis

difference between crosstalk noise and crosstalk delay

\Noise:
The term “noise” in electronic design generally means any undesirable deviation in voltage of a net that ought to have a constant voltage, such as a power supply or ground line. In CMOS circuits, this includes data signals being held constant at logic 1 or logic 0.

For noise analysis tool considers the cross-coupling between aggressor nets and victim nets.
it determines the worst-case noise bump or glitch on steady-state victim net.
Steady-state means that the net is constant at logic 1 or logic 0.
The main commands for noise analysis are the check_noise, update_noise, and report_noise commands, which operate in a manner similar to the check_timing, update_timing, and report_timing
Prime time gives the noise reports as
1.Above high
2.Above Low
3.Below Low
4. Below high
There are many different causes of noise such as charge storage effects at p-n junctions, power supply noise, and substrate noise. However, the dominant noise effect in deep-submicron CMOS circuits is crosstalk noise

Crosstalk delay: Crosstalk delay is same as noise but in this case both the nets are not in a steady state.
there is some transition happening on both the nets.
crosstalk delay depends on the propagating direction of the aggressor and victim nets which makes the transition slower or faster.

Note: for setup analysis tool add crosstalk delay to the timing path and for hold it subtract the delta delay from the cell delay.


reference: solvnet

Report global timing

Report global timing

in the latest prime time you can get global setup/hold reports as below format
Setup violations
Total reg->reg reg->out in->reg in->out
WNS -2 0.3 1.6 0.00
TNS 4 1 2 0.00
NOVP 50 10 20 0

Hold violations
Total reg->reg reg->out in->reg in->out
WNS -2 0.3 1.6 0.00
TNS 4 1 2 0.00
NOVP 50 10 20 0

Constraint Reports in PT(prime time report_constraints -all_violators)

The report_constraint command summarizes the constraint violations, including the amount by which a constraint is violated or met and the design object that is the worst violator. PrimeTime can report the maximum area of a design and certain timing constraints. It can also verify whether the netlist meets specific pin limits.

Timing Constraints

There are several types of timing constraints, such as

Maximum path delay and setup

Minimum path delay and hold

Recovery time, the minimum amount of time required between an asynchronous control signal (such as the asynchronous clear input of a flip-flop) going inactive and a subsequent active clock edge

Removal time, the minimum amount of time required between a clock edge that occurs while an asynchronous input is active and the subsequent removal of the asserted asynchronous control signal

Clock-gating setup and hold

Minimum pulse width high or low at one or several clock pins in the network

Minimum period at a clock pin

Maximum skew between two clock pins of a cell

reference solvnet/prime time

prime time sanity checks (analysis coverage)

Run link_design and resolve link errors.

Run check_timing and resolve timing check errors.

Run report_analysis_coverage and resolve untested issues.

Perform the rest of the analysis.

The report_analysis_coverage command summarizes these checks:

Setup

Hold

No-change

Minimum period

Recovery

Removal

Minimum pulse width

Clock separation (master-slave)

Clock-gating setup

Clock-gating hold

Output setup

Output hold

Maximum skew

reference solvnet/prime time

prime time flow: STA : Static timing analysis

Set search path
Set link .libs
Read ldb
Read verilog
Currenct design
Link design
Read constraints
Create clocks
I/O delays
Set uncertainty, source latency
Set clock trans
Set multy cycle path
Set false path
Set case analysis

update timing
Check timing



Read Paracitics
Check timing
Report global timing

A tie-high, tie-low circuit

Tie-high and tie-lo cells are used to avoid direct gate connection to the power or ground network. In your design, some cell inputs may require a logic0 or logic1 value. The spare cell inputs are also connected to ground or power nets, as you cannot leave them unconnected. Instead of connecting these to the VDD/VSS rails/rings, you connect them to special cells available in your library called TIE cells.(Note: All libraries may not have them).

A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage.

An integrated circuit (IC) application does not always require all of its inputs to be used. The inputs that are not used should advantageously be locked in a single, stable logic state, and should not be left floating, because inputs having unpredictable or intermediate logic states may have unpredictable and unrepeatable influences on logic outcomes. This is a major issue that IC designers strive to eliminate.



For stability, therefore, small circuits are inserted into ICs. The small circuits have at least two outputs: one that is always high and another that is always low. These circuits are then used to tie IC inputs to either a high state or a low state. By implementing these circuits, inputs that are not used are locked in a single, stable logic state.



However, various issues exist in the conventional designs of these circuits. For example, many of these circuits comprise at least four transistors, which take up valuable real estate in ICs and may require additional, costly production steps. As another example, some of the designs of these circuits comprise three transistors, but such designs typically exhibit limited tolerance to electrostatic discharge (ESD).

Therefore, desirable in the art of integrated circuit designs are improved designs with smaller circuits having increased ESD tolerance that can be used to tie-high or tie-low an unused IC input.

Why do you use them?

Gate oxide is thin and sensitive to voltage surges. Some processes does not let you connect the gates directly to power rails since any surge in voltage, like an ESD event, can damage the gate oxide. Hence tie cells, which are diode connected n-type or p-type devices are used instead.The gates won’t be connected to either power or ground directly.

That is the argument the foundries have for ESD protection against surges. Now, go check the schematic of the TIE cells in your standard cell library.. It is possible that it is just an inverter tied with input tied either to VDD(Ti-lo) or VSS (ti-high). In that case, the gate of the tie cell is still connected to power rails. However there are some uses for these types of cells. Leakage current is reduced in this configuration.Also,rewiring these in times of an ECO is easier, especially if you just want to swap 1’b1 for a 1’b0

Terminology in VLSI

ASIC

Acronym for Application Specific Integrated Circuits. A custom or semi
custom integrated circuit, such as a cell or gate array, created for a specific
application. The complexity of ASICs typically requires significant use of
CAD techniques.

Block

 Also known as functional block or module. Any block within the design
hierarchy instantiated one or more times that will be laid out separately is
referred to as a block module. Block modules are defined divisions of a chip
based on functionality and can be worked on independently of other
functional blocks.

Netlist

 A description of the circuit. The description can be a gate-level or RegisterTransfer
level (RTL) one. It can also be in different languages like Verilog
or VHDL or SPICE.

Physical Design

A portion of a chip or circuit corresponding to a block module that is laid
out separately using a Physical Design tool. It is also referred to as a
physical block, layout region, or layout block.

RTL

 Acronym for Register Transfer Level
Characterization Electrical analysis performed for the purpose of determining typical device
performance characteristics and/or parametric limits.25

CMOS

 Acronym for Complimentary Metal Oxide Semiconductor. An MOS
technology in which both P-channel and N-channel devices are fabricated
on the same die.

Die

 A single square or rectangular piece of silicon into which a specific
semiconductor circuit has been diffused.

Electromigration

 Particle migration in aluminum or copper thin-film or polysilicon
conductors at grain boundaries as a result of high current densities.
Electromigration can lead to either an open circuit condition in a conductor
or a short between adjacent connectors.

Interconnect

The metallization connecting two or more active elements on the surface of
a die; also, the wires connecting the die to the package leads.

Timing Window

Timing window specifies the interval of each circuit node at which a
transition activity is anticipated. For a single clock domain, the time interval
can lie within a clock period. There can be more than one intervals or
overlapping intervals based on complexity of path converging to the node.