finite state machine: FSM

Definition

A machine consisting of a set of states, a start state, an input, and a transition function that maps input and current states to a next state. Machine begins in the start state with an input. It changes to new states depending on the transition function. The transition function depends on current states and inputs. The output of the machine depends on input and/or current state.

There are two types of FSMs which are popularly used in the digital design. They are

• Moore machine
• Mealy machine

Moore machine

In Moore machine the output depends only on current state.The advantage of the Moore model is a simplification of the behavior.

Mealy machine

In Mealy machine the output depend on both current state and input.The advantage of the Mealy model is that it may lead to reduction of the number of states.

In both models the next state depends on current state and input. Some times designers use mixed models. States will be encoded for representing a particular state.

Representation of a FSM

A FSM can be represented in two forms:

• Graph Notation
• State Transition Table

Graph Notation

• In this representation every state is a node. A node is represented using a circular shape and the state code is written within the circular shape.
• The state transitions are represented by an edge with arrow head. The tail of the edge shows current state and arrow points to next state, depending on the input and current state. The state transition condition is written on the edge.
• The initial/start state is sometime represented by a double lined circular shape, or a different colour shade.

The following image shows the way of graph notation of FSM. The codes 00and 11 are the state codes. 00 is the value of initial/starting/reset state. The machine will start with 00 state. If the machine is reseted then the next state will be 00 state.


State Transition Table

The State Transition Table has the following columns:

• Current State: Contains current state code
• Input: Input values of the FSM
• Next State: Contains the next state code
• Output: Expected output values

An example of state transition table is shown below.


Mealy FSM

In Mealy machine the output depend on both current state and input.The advantage of the Mealy model is that it may lead to reduction of the number of states.


The block diagram of the Mealy FSM is shown above. The output function depends on input also. The current state function updates the current state register (number of bits depends on state encoding used).


The above FSM shows an example of a Mealy FSM, the text on the arrow lines show (condition)/(output). 'a' is the input and 'x' is the output.

Moore FSM

In Moore machine the output depends only on current state.The advantage of the Moore model is a simplification of the behavior.


The above figure shows the block diagram of a Moore FSM. The output function doesn't depend on input. The current state function updates the current state register.


The above FSM shows an example of a Moore FSM. 'a' is the input. Inside every circle the text is (State code)/(output). Here there is only one output, in state '11' the output is '1'.

In both the FSMs the reset signal will change the contents of current state register to initial/reset state.

State Encoding

In a FSM design each state is represented by a binary code, which are used to identify the state of the machine. These codes are the possible values of the state register. The process of assigning the binary codes to each state is known as state encoding.
The choice of encoding plays a key role in the FSM design. It influences the complexity, size, power consumption, speed of the design. If the encoding is such that the transitions of flip-flops (of state register) are minimized then the power will be saved. The timing of the machine are often affected by the choice of encoding.
The choice of encoding depends on the type of technology used like ASIC, FPGA, CPLD etc. and also the design specifications.

State encoding techniques

The following are the most common state encoding techniques used.

• Binary encoding
• One-hot encoding
• Gray encoding

In the following explanation assume that there are N number of states in the FSM.

Binary encoding
The code of a state is simply a binary number. The number of bits is equal to log₂(N) rounded to next natural number. Suppose N = 6, then the number of bits are 3, and the state codes are:
S0 - 000
S1 - 001
S2 - 010
S3 - 011
S4 - 100
S5 - 101

One-hot encoding
In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are N states then N state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. If N = 5, then the number of bits (flip-flops) required are 5, and the state codes are:
S0 - 00001
S1 - 00010
S2 - 00100
S3 - 01000
S4 - 10000

To know more about one-hot encoding click here.

Gray encoding
Gray encoding uses the Gray codes, also known as reflected binary codes, to represent states, where two successive codes differ in only one digit. This helps is reducing the number of transition of the flip-flops outputs. The number of bits is equal to log₂(N) rounded to next natural number. If N = 4, then 2 flip-flops are required and the state codes are:
S0 - 00
S1 - 01
S2 - 11
S3 - 10

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc.

Wafer related definitions: Wafer sawing

Wafer sawing

 

Wafer sawing is the last back-end operation in which a processing error can convert an entire $50,000 wafer into thousands of pieces of expensive scrap. Proper dicing of wafers requires experience, judgement, and high-performance equipment. Successful sawing requires selecting the correct saw blade from dozens of possibilities and finding the proper combination among dozens of control settings. Wafer thickness and composition, the width of the saw streets, and the desired die size must be considered when selecting sawing parameters. The wrong blade or the wrong combination of parameters can ruin the wafer.

The continuing shrinkage of semiconductor devices toward smaller feature size and higher density is raising the hurdle of sawing. Wafers are designed to hold as many die as possible. Producing a wafer is a fixed cost, so more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow “streets,” which are the cut lines for singulating the die. The narrower the streets, the more die – and the more challenging the sawing.

While several new singulation technologies are being developed or in limited use, ordinary silicon wafers, which comprise more than 90% of wafer volume, are sawn with a diamond saw blade. Selecting the proper saw, diamond blade, and mounting tape are three keys to success.
Dicing Saws

Silicon dicing saws offer a wide variety of models with many options. Options include manual or fully automated operation; single-blade or multi-blade cutting; cutting in one direction only or bi-directional; blade mounting on a 2- or 4-in.-diameter hub; cooling water flow from a single jet or from multiple jets; and spindle rotational speeds ranging from 1,000 to 60,000 rpm.

Figure 1 shows an operating saw, showing the rotating saw blade and the spray of cooling water.

Figure 1. Close-up of an operating saw, with cooling water spraying at the top of the rotating blade and the wafer. Photo courtesy of Disco.Click here to enlarge image

Post-saw cleaners, which remove the residual silicon dust, may be a part of the saw or standalone equipment. Automatic blade “dressing,” to maintain the cutting surface, may be included in the saw.

A semiconductor manufacturer may routinely saw large quantities of wafers. Manufacturers have the advantage of a limited family of products and materials, however, so that they can standardize their sawing equipment and processes. As a wafer service provider, every month we must saw wafers with hundreds of different part types from any of 30 wafer manufacturers. We use two types of saws to deal with this variety: semiautomatic and fully automated machines.

The semiautomatic saw dices single wafer orders that have low to moderate sawing complexity. This saw has one cooling jet, a single blade on a 2-in. hub, and a maximum spindle speed of 40,000 rpm. The operator programs the saw and must monitor the sawing, intervening as needed.

In summary, wafer sawing remains both an art and a science. For best results, both high-performance equipment and the proper materials must be combined with expert human judgement and experience.

 

 

 

seal ring

  

1. A wafer edge seal ring structure comprising:

a substrate;

• a layer of polysilicon formed over said substrate having a circumferential recess thereat between about 1.6 to 2.0 Å from the edge of said substrate;
• a first interlevel dielectric layer deposited on said layer of polysilicon having a circumferential recess thereat between about 1.0 to 1.5 mm from the edge of said substrate;
• a first metal layer deposited on said first interlevel dielectric having a circumferential recess thereat between about 2.5 to 3.1 mm from the edge of said substrate;
• a second interlevel dielectric deposited on said first metal layer having a circumferential recess thereat between about 2.0 to 2.6 mm from the edge of said substrate;
• a second metal layer deposited on said second interlevel dielectric layer having a circumferential recess thereat between about 1.5 to 2.0 mm from the edge of said substrate;
• a third interlevel dielectric deposited on said second metal layer having a circumferential recess thereat between about 3.0 to 3.5 mm from the edge of said substrate;
• a third metal layer deposited on said third interlevel dielectric layer having a circumferential recess thereat between about 2.5 to 3.1 mm from the edge of said substrate; and
• a passivation layer deposited on said third metal layer.

2. The structure of claim 1, wherein said substrate is silicon.

3. The structure of claim 1, wherein said substrate contains semiconductor devices.

4. The structure of claim 1, wherein said first interlevel dielectric layer is BPTEOS.

5. The structure of claim 4, wherein said first BPTEOS layer has a thickness between about 9,000 to 10,000 Å.

6. The structure of claim 1, wherein said first metal layer is aluminum-copper.

7. The structure of claim 6, wherein said first metal layer has a thickness between about 5,000 to 5,600 Å.

8. The structure of claim 1, wherein said second interlevel dielectric layer is a sandwich dielectric structure.

9. The structure of claim 8, wherein said sandwich dielectric structure has a thickness between about 8,000 to 10,000 Å.

10. The structure of claim 1, wherein said second metal layer is aluminum-copper.

11. The structure of claim 10, wherein said second metal layer has a thickness between about 5,000 to 6,000 Å.

12. The structure of claim 1, wherein said third interlevel dielectric layer is SOG.

13. The structure of claim 12, wherein said third SOG layer has a thickness between about 8,000 to 10,000 Å.

14. The structure of claim 1, wherein said third metal layer is aluminum-copper.

15. The structure of claim 14, wherein said third metal layer has a thickness between about 8,000 to 8,200 Å.

16. The structure of claim 1, wherein said passivation layer is a photosensitive polyimide.

17. The structure of claim 16, wherein said polyimide has a thickness about 3.0 micrometers.

Copper Piller

Cu-Piller 

Copper pillar bump(CPB) technology is to produce a bump on the surface of Flip chip package which has the electric and heat conductivity and the resistance to electrical migration. It’s different from the traditional solder bump. Each heat dissipation copper pillar is the same as the micro-solid heat pump. The heat dissipation bumping can integrate to a part of the standard flip chip package and is connected with the electric bumping (uses on power supply、grounding and signal). The technique provides the new heat dissipation function of the electronic component which can also integrate with transistor, resistor and capacitor to the circuit design.
This technique will extend the traditional solder bumping application and provides flip chip package component to initially cooling function. Its electric generate ability has copper pillar used the recycle energy. Before this technique, the solder bumping can only provide the mechanical heat dissipation function.

 

Features 

Good Heat dissipation
lower electrical resistance/inductivity
lower thermal resistance
better resistance to electrical migration
Offer the more fine pitch
Comply with RoHS specification - Cu post + SnAg cap

 

Application: 

High pin logic IC
Memory & Mobile Apparatus
LED Sub-mount
Automotive Electronic Component
Bio-Medical devices

 

Process Flow: