The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and the Encounter Digital Implementation (EDI) System. Whether you're performing floorplanning in Virtuoso (schematic-driven flow) or EDI System (netlist driven flow), OA allows you take advantage of interoperability features such as seamlessly defining and passing routing constraints. The Mixed Signal Interoperability Guide (Cadence Online Support account required) is the resource I turn to frequently when I have questions on the mixed-signal flow. Formal training is also available through the Analog-on-Top Mixed-Signal Implementation class.
In this blog I want to focus on data preparation and highlight the steps involved to create a common PDK to be used by Virtuoso and EDI System. This involves translating the LEF files to OA, then reconciling the differences between your base PDK and the OA database created from the LEF. Once these differences are resolved, I explain how to load the design into EDI System references the OA libraries.
Converting LEF to OA
The first step is to create a LEF-compatible PDK which Virtuoso and EDI System can use. This is typically defined in 1 of 2 ways:
1. A single PDK containing the base PDK information plus the LEF rules and vias required for physical design.
A single PDK is not flexible. For example, if you have to add a custom via or routing constraint you must modify this main PDK which may cause problems for other users.
2. Define the LEF rules and vias in an Incremental Technology Database (ITDB) which references the base PDK.
An ITDB is more flexible because updates can be made directly to the ITDB without effecting the base PDK. You can also define multiple ITDBs which reference the same base PDK.
The ITDB is typically created by converting the technology LEF to OA using the lefin command found in the Virtuoso installation. To create an ITDB from tech.lef referencing the basePDKLib you would run:
lefin -lef tech.lef -lib techLib -refLib basePDKLib
The LEF files defining the standard cells, hard macros and IO cells are then converted to OA using lefin:
lefin -lef stdcells.lef -lib macroLib -refLib techLib
lefin -lef memories.lef -lib macroLib
lefin -lef io.lef -lib macroLib
After the LEF files are transferred to OA run verilogAnnotate to indicate the bit order for busses:
verilogAnnotate -refLibs macroLib -verilog macros.v -refViews layout
Reconciling the ITDB with the Base PDK
Often the LEF technology data and the base PDK are not consistent and you must reconcile their differences. For example, layer names, units or manufacturing grid may differ. For more details on creating a LEF-compatible PDK see the application note Open Access Reference Library Import on Cadence Online Support.
Another useful way to debug differences is compare your original technology LEF to the LEF generated from the OA tech file you've created. You can use the write_lef_library command to compare these LEFs. write_lef_library writes out LEF syntax in a consistent order for easy comparison using the diff command. Below is an example flow to compare the LEF files. See the next section for details on specifying the variables to import an OA based library.
Validation of LEF versus OA
Generate a LEF based on your original tech LEF:
# setup Tcl variables for reading the LEF based design
init_design
write_lef_library from_lef.lef
exit
Generate a LEF based on the OA technology file:
# setup Tcl variables for OA based library using the same Verilog
# and timing libraries
init_design
write_lef_library from_oa.lef
exit
Now run diff to compare the LEF files and investigate the differences:
diff from_lef.lef from_oa.lef
Look for things such as rules and vias defined in one file but not the other. Also, review rules which are the same but have different values specified.
Reading in the Design
After all the LEF libraries are converted you are ready to read in the design. This can be done by reading in the OA libraries + Verilog or read the libraries and design from OA.
Reading in OA Libraries and Verilog Netlist
Following are the variables to set to read in a design using OA libraries and a Verilog netlist:
# Library variables:
set init_oa_ref_lib {techLib macroLib}
set init_layout_view {layout}
set init_abstract_view {abstract}
# Design variables:
set init_verilog {netlist.v}
set init_design_settop 0
set init_top_cell {top}
# Set other init_design variables for global vars, timing, etc.
init_design
# Save the design to OA using saveDesign {lib cell view}
saveDesign -cellview {designLib top preplace}
Reading in OA Libraries and OA Design
Following are the variables to set to read in a design using OA libraries and OA design:
# Library variables:
set init_oa_ref_lib {techLib macroLib}
set init_layout_view {layout}
set init_abstract_view {abstract}
# Design variables:
set init_design_netlisttype {OA}
set init_oa_design_lib {designLib}
set init_oa_design_cell {top}
set init_oa_design_view {layout}
# Set other init_design variables for global vars, timing, etc.
init_design
# Save the design to OA using saveDesign {lib cell view}
saveDesign -cellview {designLib top preplace}
And there you go. I hope this overview helps you understand the data preparation steps involved creating a LEF-compatible PDK and encourages you to utilize OA to take advantage of Virtuoso and EDI System's interoperability. Be sure to leverage the resources I reference above to help your transition go smoothly.
Reference:
http://www.cadence.com/
