Timing Models (ETM, QTM, ILM)

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Timing Models:

If we want to perform static timing analysis on a chip using PrimeTime, every leaf cell must have a timing model. For static timing purposes, a leaf cell can be a simple macro cell (such as a NAND, NOR, or flip-flop) or a complex block (such as a RAM or microprocessor).

In Flat full chip timing analysis we need to read gate level netlist along with SPEF/SDF, timing libraries and constraints.Using this approach designers should wait till all blocks completion prior to performing full chip timing.

Hierarchical STA flow allows you to partition different blocks using timing models which Should completely model the full input/output timing characteristics without requiring the complete netlist of the block and Do not model every path in the block.

 Internal register to register paths are generally discarded, as these paths can be analyzed at the block level using the complete gate-level netlist.

Hierarchical STA flow has several benefits. Hierarchical STA reduces runtime and memory usage compared to flat STA. The actual run time savings depend on the design complexity.

Types of Timing Model: 

1. ETM Extracted Timing Models: 
2. ILM Interface Logic Models
3. QTM Quick Timing Model

ETM (Extracted Timing Models):

The Extracted Timing Model (ETM) is an abstraction of the block using sequential and combinational timing arcs. NLDM lookup tables are extracted for each of the timing arcs whose delay is a function of input transitions and output loads, which makes the ETM usable with different input transition times and different output loads.

Using ETMs to abstract the timing model of a complex block or IP hides the detailed design implementation information. This usage model is ideal for IP providers.

1. Block based model (.lib)
2. Contents of block are hidden
3. Original netlist replaced by model containing timing arcs for block interfaces.
4. NLDM lookup tables are extracted for each of the timing arcs.
5. These arcs whose delay are a function of input transition and output load. This makes ETM usable with different input transition times and different output loads.
6. Multiple modes per model
7. Single PVT per model

Used for implementation (not sign-off) of IP models. Here the content are protected because the model contains abstracted timing information, without any netlist information.

ETM model Illustration:

QTM (Quick Timing Models):

In the early stages of the design cycle, if a block does not yet have a netlist, you can use a quick timing model to describe its initial timing. Later in the cycle, you can replace each quick timing model with a netlist block to obtain more accurate timing

Interface Logic Models (ILMs):

Combinational paths from the input ports that do not encounter a sequential element and pass directly to an output port , An ILM is a partial netlist of the block that includes the boundary logic, but hides most of the internal register-to-register logic, for full-chip analysis, An interface logic model (ILM) is a partial netlist that contains only the interface logic of a block. The ILM contains :

1. The combinational logic from each input port to the first stage of sequential elements of the block
2. The combinational logic from the last stage of sequential elements to each output port of the block
3. The clock paths to these sequential elements 
4. Combinational paths from the input ports that do not encounter a sequential element and pass directly to an output port

Difference between ILM and ETM :

Both ETMs and ILMs can be used in a hierarchical static analysis flow when flat analysis is not possible because of runtime and/or memory usage. An ILM offers more visibility into the netlist, which can result in easier verification, but provides less IP protection.

ETM is just like .lib means we have timing information till the pins not to the first level ( I mean to say the first gate of FF) but if we want to do timing analysis between the partition level FF to FF then we can do that with ETM.

 ILM model.we can see the timing logic to the first level and vise-versa from the last level to the output pins but we can not optimize anything inside the partition.

Reference: Synopsis solvnet

HFN ( High Fanout Net Synthesis )

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 Fanout:

Fanout is the number of gate inputs to which the output can be safely connected. i.e., The load that a gate output can drive. The maximum fanout of an output measures it's load-driving capability. Fanout belongs to the output.

High fanout net synthesis :

High Fanout Nets are the nets which drive more number of load. High fanout nets other than clocks are synthesized at the placement stage. In logic synthesis, high fanout nets like reset, scan enable etc are not synthesized. You should verify that the SDC used for PnR should not have any set_ideal_network or set_dont_touch commands on these signals. Also, make sure you set an appropriate fanout limit for your library using the command set_max_fanout.

set_max_fanout during synthesis this means we tell to the synthesis tool that more than the max_fanout number treat it as High fanout net.

Generally at placement step HFNS performed. HFNS can also be performed at synthesis step using Design Compiler. But it's not good idea, Buffers will be removed during PD and again HFNS is performed. It's very time consuming process. So HFNS at synthesis step is not recommended. HFNS at synthesis step gives an idea whether HFN are present in data path or not. Generally HFN are present in clock paths, rest, enable  and scan paths. 

Care that should taken during HFNS:

1. Make sure an appropriate fanout limit is set using

set_max_fanout command

2. Verify the SDC used for PD should not have

set_ideal_network or set_dont_touch commands on High  Fanout Nets.

3. Use ideal clock network - As clock nets are synthesized separately during Clock Tree Synthesis (CTS) step, we set clock network as ideal network.

Blockages and Halo

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Blockages: 

Placement blockages prevent the placement engine from placing cells at specific locations. Routing blockages block routing resources on one or more layers and it can be created at any point in a design flow. In general placement blockages are created at floor planning stage and routing blockages are created before using any routers. It acts like guidelines for placement of standard cells. Blockages will not be guiding the tool to place the standard cells at some particular area, but it won’t allow the tool to place the standard cell in the blocked areas (in both placement and routing blockages). This is how the blockages acts like guidelines for standard cell placement. During the CTS process (Clock Tree Synthesis) in order to balance the skew, more number of buffers and inverters are added and blockages are used to reserve space for buffers and inverters.

Placement blockages uses: 

1. Define std-cells and macro area
2. Reserve channels for buffer insertion
3. Prevent cells from being placed at or near macros
4. Prevent congestion near macros

Soft (Non buffer blockage) : 

Only buffers can be placed and standard cells cannot be placed.

Hard (Std-cell blockage):

Blocks all std-cells and buffers to be placed. Std-cell blockages are mostly used to:

Avoid routing congestion at macro corners

Restrict std-cells to certain regions in the design

Control power rails generation at macro cells

Partial blockages: 

By default a placement blockage has a blockage factor of 100%. No cells can be placed in that area, but flexibility of blockages can be chosen by partial blockages. To reduce placement density without blocking 100% of the area, changing the blockage factor of an existing blockage to lower value will be a better option.

Halo cells ( halo ) Keepout Margin : 

It’s the region around the boundary of fixed macros in design in which no other macros or std-cells can be placed. It allows placement of buffers and inverters in its area. Pictorial representation of halo is mentioned in the above figure, 

Halos of adjacent macros can overlap; there the size of halo determines the default top level channel size between macros. Prevent cells from being placed at or near the macros.

If the macros are moved from one place to another, hallows will also be moved.