SDC: Synopsys Design Constraints

SDC:  Synopsys Design Constraints: SDC has the following content:

1. CLOCK DEFINITIONS:Create Clock Period.
2. Generated Clock Definitions
3. Input Delay
4. Output Delay
5. I/O delay
6. Max delay
7. Min Delay
8. Multi cycle path
9. False path
10. Half cycle path
11. Disable timing arcs
12. Case Analysis

Clock Definition: 

1. create_clock
2. create_generated_clock

The above two are the most important statements in the SDC, there must be a proper clock definition. If these clock definitions are proper you might have to talk to the Synthesis Guy or look back to the synthesis stage

if you have many clocks (~100 clocks including generated), then it must to have their proper information to balance and fix timing.

Clock uncertainty: 

1. set_clock_uncertainty
2. set_clock_transition -rise/fall 

False Paths

1. A path that can never be sensitized in the actual circuit
2. These paths are those that are logically/functionally impossible
3. The goal in static timing analysis is to do timing analysis on all “true” timing paths, these paths are excluded from timing analysis.

1. set_false_path statements 
2. set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
3. set_false_path -from [get_ports TX_REG1]

Multicycle path: 

1. Those paths that require more than one clock period for execution are called as multi-cycle paths.
2. It’s essential that multi-cycle paths in the design be identified both for synthesis and STA.

set_multicycle_path 1 -hold -end -from ff1/CP -to ff2/D

Operating conditions

“set_operating_conditions” statements specify the operating conditions for the design.

Specifying Ideal Networks – No optimizations required

set_input_delay/set_output_delay

Clock skews (timing skew)

Clock signal in synchronous circuits arrives at different components at different times.

Clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Reasons for the Skew:

Wire-interconnect length
Temperature variations
Variation in intermediate devices
Capacitive coupling
Material imperfections

Two Types of Clock Skew:

Negative skew
Positive skew

Positive skew:

Occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Negative skew:

Is the opposite:- the receiving register gets the clock earlier than the sending register.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Notes:
Less clock latency:
Lesser number of clock buf/inv
Less power consumption
Less Area