There are different methods of Increasing and Decreasing the Delay in the circuit to fix these type of violations?
Ways To Fix Setup violation:
Setup violations are essentially where the data path is too slow compared to the clock speed at the capture flip-flop. With that in mind there are several things a designer can do to fix the setup violations.
Method 1 : Reduce the amount of buffering in the path.
It will reduce the cell delay but increase the wire delay. So if we can reduce more cell delay in comparison to wire delay, the effective stage delay decreases.
Method 2 : Replace buffers with 2 Inverters place farther apart
Adding 2 inverters in place of 1 buffer, reducing the overall stage delay.
Adding inverter decreases the transition time 2 times then the existing buffer gate. Due to that, the RC delay of the wire (interconnect delay) decreases.
As such cell delay of 1 buffer gate ≈ cell delay of 2 Inverter gate
So stage delay (cell delay + wire delay) in case of single buffer < stage delay in case of 2 inverter in the same path.
You will get the clear understanding by following figure and you can refer the first post to understand how transition time varies across the wire.
Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.
Low Vt decrease the transition time and so propagation delay decreases.
HVT/NVT/LVT type cells have same size and pin position. In both leakage current and speed, LVT>NVT, HVT. So replace HVT with NVT or LVT will speed up the timing without disturb layout.
Negative effect: Leakage current/power also increases
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Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)
Explained the basic and details in the previous post Note: Normally larger cell has higher speed. But some special cell may have larger cell slower than normal cell. Check the technology library timing table to find out these special cells. Increasing driver is very commonly used in setup fix.
Negative effect: Higher power consumption and more area used in the layout.
Method 5 : Insert Buffers
Some time we insert the buffer to decrease over all delay in case of log wire.
Inserting buffer decreases the transition time, which decreases the wire delay.
If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all delay decreases.
Negative Effect: Area will increase and increase in the power consumption.
Inserting buffer decreases the transition time, which decreases the wire delay.
If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all delay decreases.
Negative Effect: Area will increase and increase in the power consumption.
Method 6 : Inserting repeaters:
Concepts of Repeaters are same as I have discussed in “Inserting the Buffer” (above point). Just I am trying to explain this in a different way but the over concept are same.
Long distance routing means a huge RC loading due to a series of RC delays, as shown in figure. A good alternative is to use repeaters, by splitting the line into several pieces. Why can this solution be better in terms of delay? Because the gate delay is quite small compared to the RC delay.
In case of Interconnect driven by a single inverter, the propagation delay become
Tdelay= tgate+ nR.nC = tgate + n2RC
If two repeaters are inserted, the delay becomes:
Tdelay=tgate (delay of inverter) + 2tgate (delay of repeater) +3RC = 3tgate + 3RC
So you can see how RC delay is impacting in case of non-repeater in the circuit.
Consequently, if the gate delay is much smaller than the RC delay, repeaters improve the switching speed performances, at the price of higher power consumption.
Below figure helps you to understand the practical use of this.
Long distance routing means a huge RC loading due to a series of RC delays, as shown in figure. A good alternative is to use repeaters, by splitting the line into several pieces. Why can this solution be better in terms of delay? Because the gate delay is quite small compared to the RC delay.
In case of Interconnect driven by a single inverter, the propagation delay become
Tdelay= tgate+ nR.nC = tgate + n2RC
If two repeaters are inserted, the delay becomes:
Tdelay=tgate (delay of inverter) + 2tgate (delay of repeater) +3RC = 3tgate + 3RC
So you can see how RC delay is impacting in case of non-repeater in the circuit.
Consequently, if the gate delay is much smaller than the RC delay, repeaters improve the switching speed performances, at the price of higher power consumption.
Below figure helps you to understand the practical use of this.
Method 7 : Adjust cell position in layout.
Let’s assume there are 2 gate (GATE A and GATE B) separated by 1000um. There is another GATE C placed at the distance of 900um from GATE A.
If we re-position the GATE C at 500um from GATE A (center of GATE A and B), overall delay between GATE A and B decreases.
You will get the clear understanding by first post and the following diagram.
Note: The placement in layout may prevent such movement. Always use layout viewer to check if there are any spare space to move the critical cell to an optimal location.
Method 8 : Clock skew:
Many designers say that dont touch the clock path, but I say do whatever you want to do without affecting any other thing.
By delaying the clock to the end point can relax the timing of the path, but you have to make sure the downstream paths are not critical paths.
Related to clock skew basic – I will discuss that in SI section.
By delaying the clock to the end point can relax the timing of the path, but you have to make sure the downstream paths are not critical paths.
Related to clock skew basic – I will discuss that in SI section.
This can be used for hold fixing as well
2 Ways to Fix Hold Violations:
Hold violation is the opposite of setup violation. Hold violation happen when data is too fast compared to the clock speed. For fixing the hold violation, delay should be increases in the data path.
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be reduced.
The designer needs to simply add more delay to the data path. This can be done by
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be reduced.
The designer needs to simply add more delay to the data path. This can be done by
Method 1 : By Adding delays.
Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold violation.
Note: The hold violation path may have its start point or end point in other setup violation paths. So we have to take extra care before adding the buffer/delay.
E.G. if the endpoint of hold violation path has setup violation with respect to some other path, insert the buffer/delay nearer to start point of hold violation path. Else the setup violation increases in other path.
if the start point of hold violation path has setup violation with respect to some other path, insert the buffer/delay nearer to end point of hold violation path. Else the setup violation increases in other path.
I am sure you may be asking what is this and why?
Below figure and explanation can help you to understand this.
From below figure, you can also conclude that don’t add buffer/delay in the common segment of 2 paths (where one path has hold violation and other setup violation).
